SHF: Small: Modeling and Preventing Electromigration-Caused Degradation in Cu Dual Damascene Scaled Interconnects

现代计算机芯片包含数十亿个通过电线连接的微小晶体管。大规模集成电路(IC)在其生命周期中容易磨损和退化。当电流在微小导线中流动时，运动的电子碰撞成扩散的金属原子，引起离子的逐渐运动。这种由电流引起的物质传输称为电迁移(EM)。电迁移现象是互连退化的主要来源。随着时间的推移，电磁可能会导致断线或短路，从而导致电路故障。更大的电流密度、导线几何或材料缺陷以及更高的温度都会使EM恶化。过去，互连制造的改进与互连规模保持同步，并允许通过限制电流密度来相对简单地遏制EM。互联互通规模现在正接近现有模型和假设不再有效的地步。同时，芯片S的导热系数下降，而片上导线的载流密度和工作功率稳步增加，导致明显的自热现象。这些影响再次将EM推到了风口浪尖，并导致它现在对工作中的芯片构成了严重的可靠性威胁。迫切需要开发一种全面的芯片级EM分析工具。PI建议开发一个物理EM模拟器，以了解各种互连配置中的故障机制。PI将使用模拟器来制定线路故障时间估计的指标。PI建议开发互连故障的统计模型和电迁移退化效应的芯片级分析器。预期寿命短于预期寿命的互连可以修改。这项工作通过解决可能影响集成电路规模化趋势的关键研究问题来支持美国半导体行业。建议的技术将对设计者有用，因为最糟糕的电路退化条件发生在芯片的可以识别和解决的小区域。此外，即将开发的工具还可能帮助工艺工程师研究新材料对电路级特性的影响。拟议的研究活动还将作为培训博士生的平台，这些博士生将为在现代工业或学术界工作做好准备。

Modern computer chips contain billions of tiny transistors connected by wires. The massively integrated circuits (ICs) are prone to wear out and degradation during their lifetimes. When electric current flows in a microscopic wire, the moving electrons collide into diffusing metal atoms and cause a gradual ion movement. This current-flow-induced material transport is called electromigration (EM). The electromigration phenomenon is a major source of interconnect degradation. Over time EM may cause wire breaks or shorts leading to circuit malfunction. Greater current densities, wire geometry or material imperfections, and increased temperature worsen EM. In the past, improvements in interconnect manufacturing kept pace with interconnect scaling and allowed for relatively simple ways of keeping EM at bay by capping current densities. Interconnect scaling is now approaching the point where the existing models and assumptions are no longer valid. At the same time chip?s thermal conductivity decreases while the density of currents carried by the on-chip wires and the operating power steadily increase causing significant self-heating. These effects bring again EM to the forefront and cause that it now poses a serious reliability threat for working chips. There is an urgent need to develop a comprehensive chip-level EM analysis tool. The PI proposes to develop a physical EM simulator to understand failure mechanisms in various interconnect configurations. The PI will use the simulator to develop metrics for wire time-to-failure estimates. The PI proposes to develop statistical models of interconnect failure and a chip-level analyzer of electromigration degradation effects. Interconnects whose expected lifetimes are shorter than desired can be modified. The will develop such modification strategies as well.This work supports the US semiconductor industry by addressing a vital research problem that may affect the integrated circuits scaling trends. The proposed techniques would be useful for designers because the worst circuit degradation conditions occur in small regions of the chip that can be identified and resolved. In addition, the tools to be developed may also help process engineers to study the effects of new materials on circuit level properties. The proposed research activities will also serve as a platform for training PhD students who will be well prepared to work in modern industry or academia.