SHF: Small: Arbitration, Coherence, and Consistency for Nanophotonic Multicore Processors

近年来，微处理器设计行业已经积极过渡到芯片多处理器设计，其中半导体制造工艺的持续扩展提供了额外的设备资源，致力于提供每个芯片不断增加的处理器内核数量。这些核心被期望维护一个共享内存的视图，方便程序员和用户使用；也就是说，内存内容必须在整个芯片上以连贯一致的方式更新。类似地，多个处理核心必须协调它们对共享资源的访问，如输入/输出子系统以及与其他芯片和主存储器的片外连接。为此类活动提供可扩展且低开销的通信基板或片上网络是当今设计人员面临的最紧迫挑战之一。现有的和提出的设计正在适应许多技术和从先前的片外网络中吸取的经验教训，但是考虑到电子和纳米光子片上网络中存在的完全不同的机会和限制，这些解决方案还远远不够理想。该项目研究了用于通信和协调多个片上处理器核心活动的新型片上网络和硬件协议。这些网络和协议提供了高度可扩展的性能，同时最大限度地减少了功耗和面积开销，从而使处理器芯片能够提供前所未有的性能水平。研究工作的重点是用封装在3D芯片堆栈中的纳米光子器件构建的网络，重点是基于高速光学机制的高效仲裁协议，以及依赖于消息内容编码的无仲裁实现，即使在通信信道处于竞争状态时也能实现稳健的传输。该项目还展示了如何利用光片上网络的优势——超低延迟、大带宽、超快速的全球协调和共识——来简化硬件协议，从而提供连贯一致的内存视图。如果在多核芯片互连的设计和在线管理方面没有显著的创新，未来纳米技术的持续设备缩放可能不再提供实用或性能方面的可观回报。因此，微处理器行业，乃至整个计算机行业都面临着严峻的挑战，即如何维持40年来以增长为基础的商业模式。这项研究具有广泛的行业和经济范围的影响，因为它有助于解决或避免这些挑战

In recent years, the microprocessor design industry has made an aggressive transition to chip-multiprocessor designs, where additional device resources provided by continued semiconductor fabrication process scaling are dedicated to providing ever-increasing numbers of processor cores per die. These cores are expected to maintain a view of shared memory that is easy for programmers and users to work with; that is, the memory contents must be updated only in ways that are coherent and consistent across the whole chip. Similarly, the multiple processing cores must coordinate their accesses to shared resources like input/output subsystems as well as off-chip connectivity to other chips and main memory. Providing a scalable and low-overhead communication substrate, or network on chip, for such activities is one of the most pressing challenges faced by designers today. Existing and proposed designs are adapting numerous techniques and lessons learned from prior off-chip networks, but these solutions are far from ideal given the radically-different opportunities and constraints that exist in both electrical and nanophotonic on-chip networks.This project investigates novel on-chip networks and hardware protocols for communicating and coordinating the activities of multiple on-chip processor cores. These networks and protocols provide highly-scalable performance while minimizing power and area overheads, hence enabling processor chips that deliver unprecedented levels of performance. The research work is focused on networks built with nanophotonic devices packaged in a 3D chip stack, with an emphasis on efficient arbitration protocols based on high-speed optical mechanisms as well as arbitration-free implementations that rely on coding of message contents to enable robust delivery even when the communication channel is under contention. The project also shows how to utilize the benefits of optical on-chip networks--ultra-low latency, massive bandwidth, and ultra-fast global coordination and consensus--to streamline the hardware protocols that provide a coherent and consistent view of memory.Without dramatic innovations in the design and online management of multicore chip interconnects, the continued device scaling of future nanometer technologies may no longer provide substantial returns in utility or performance. As a result, the microprocessor industry, and by extension, the computer industry as a whole faces a serious challenges in maintaining the growth-based business model that has sustained it for four decades. This research has broad industry- and economy-wide impact since it helps to address or avert these challenges