SHF: Small: A Cross-Layer Modeling and Optimization Framework Targeting FinFET-based Designs Operating in Multiple Voltage Regimes

最近的研究强调了节能计算对于保持信息技术的进步和应对关键的社会挑战的重要性。本项目将研究横跨计算堆栈和基础设施多层的整体电源优化和管理解决方案的探索，这将更好地提供实现能源效率最大化的现有机会。这项研究将在亚10 nm器件设计、建模和优化、标准单元库设计和表征、电路速度与能效与可靠性交易空间探索以及芯片级别的异构性建模方面推进最先进的技术。这项研究中的挑战和机遇将为开发设计未来节能计算系统和确保信息技术生态系统可持续性所需的许多技术和方法提供方向。该项目加强的教育、推广和培训计划将包括开发新的教育模块，招收少数族裔和代表性不足的学生，以及为本科生提供本科生学习和研究实习机会。从技术角度来看，该项目将在两个跨层边界进行创新：(I)技术和电路，(Ii)电路和建筑。更准确地说，研究的第一个重点将是开发具有高能效、快速开关速度和可靠性的深度规模化(多栅)CMOS器件和逻辑单元库。第二个目标是低动态和待机电源电路的设计，能够在多种电压模式下稳健和能量延迟优化操作的电路设计，以及有效的芯片级电源管理手段。为了实现这些研究目标，将开发分析和模拟工具来表征深尺寸(例如，亚10 nm)FinFET器件的特性，如离子/离子关闭比、能源效率和变化容忍度。此外，还将探讨如何使用这些新器件来设计能够在低(接近阈值)和高(超阈值)电源电压下无缝运行的存储器和逻辑单元。最后，我们将讨论在电路结构和架构模板的建模、部署和重新配置方面的关键挑战，以提高片上系统设计的整体能效。

Recent studies emphasize the importance of energy-efficient computing for sustaining advancements in information technology and addressing critical societal challenges. The exploration of holistic power optimization and management solutions that cut across multiple layers of the computing stack and infrastructure to be studied in this project will better enable available opportunities for maximizing energy efficiency. The research will advance the state-of-the art in sub-10nm device design, modeling, and optimization, standard cell library design and characterization, circuit speed vs. energy efficiency vs. reliability trade space exploration, and heterogeneity modeling at the chip level. The challenges and opportunities in this research will provide directions for developing many of the technologies and approaches that are needed to design energy-efficient computing systems of the future and ensure sustainability of the information technology ecosystem. Education, outreach, and training programs enhanced by this project will include development of new educational modules, recruitment of minority and under-represented students, as well as undergraduate learning and research internship opportunities for undergraduates.From a technical standpoint, this project will innovate at two cross-layer boundaries: (i) Technology and Circuits, and (ii) Circuits and Architectures. More precisely, a first thrust of the research will focus on developing deeply-scaled (multi-gate) CMOS devices and logic cell libraries that offer high energy efficiency, fast switching speed, and reliability. A second thrust targets the design of low dynamic and standby power circuits, circuit designs capable of robust and energy-delay optimal operation in multiple voltage regimes, and means for effective chip-level power management. To accomplish these research objectives, analysis and simulation tools will be developed to characterize properties such as Ion/Ioff ratio, energy efficiency, and variation tolerance of the deeply-scaled (e.g., sub-10nm) FinFET devices. In addition, questions of how the new devices can be used for designing memory and logic cells that can seamlessly operate at low (near-threshold) and high (super-threshold) supply voltages will be explored. Finally, key challenges in modeling, deployment, and reconfiguration of circuit fabrics and architectural templates to improve the overall energy efficiency of system-on-chip designs will be addressed.