SaTC: STARSS: Trojan Detection and Diagnosis in Mixed-Signal Systems Using On-The-Fly Learned, Precomputed and Side Channel Tests

硅制造外包的使用使得硬件容易受到恶意漏洞的影响，这种恶意漏洞被称为特洛伊木马，可以导致集成电路（IC）在现场失效，类似于病毒在软件中的表现方式。虽然近年来在木马检测和诊断方面取得了重大进展，但高分辨率木马检测一直受到硅制造工艺变异性增加的阻碍，这使得木马隐藏在工艺变异性效应所必需的设计保护带后面。本研究的主要目标是开发技术、算法和支持基础设施，用于检测、诊断和减轻各种电路中的木马的影响，这些电路在现场部署后，在存在过程可变性影响的情况下，可能导致系统故障。混合信号和数字电路的底层木马检测技术使用测试刺激优化算法，最大限度地提高了应用于恶意硬件木马存在的测试的灵敏度。这些算法由硬件支持，以便将测试交付给现场易受攻击的硬件设计。由于恶意插入芯片设计的漏洞的性质尚不清楚，因此研究人员使用实时学习算法来改进应用测试，以暴露插入木马的影响。此外，应用预先计算和侧通道测试可将整体测试效率提高到现有方法的30倍。这些技术将大大提高美国工业和政府知识产权的安全性，并防止外部第三方篡改美国芯片设计。

The use of outsourcing in silicon manufacturing has rendered hardware susceptible to malicious bugs, called Trojans, that can cause an Integrated Circuit (IC) to fail in the field, similar to the way viruses manifest themselves in software. While there has been significant inroads into Trojan detection and diagnosis in the recent past, high-resolution Trojan detection has been hampered by the increased variability in silicon manufacturing processes, allowing Trojans to hide behind the design guardbands necessitated by process variability effects. The key objective of this research is to develop techniques, algorithms and support infrastructure for detecting, diagnosing and mitigating the effects of Trojans in a variety of circuits that can cause system malfunction after deployment in the field, in the presence of process variability effects.The underlying Trojan detection techniques for both mixed-signal and digital circuits use test stimulus optimization algorithms that maximize the sensitivities of the tests applied to the presence of malicious hardware Trojans. Such algorithms are supported by hardware for delivering the tests to vulnerable hardware designs in the field. Since the nature of bugs inserted maliciously into chip designs is not known apriori, the investigators use on-the-fly learning algorithms to refine the applied tests to expose the effects of inserted Trojans. In addition, precomputed and side-channel tests are applied to increase overall test effectiveness by up to 30X over existing methods. These techniques will enable significantly increased security of US industrial and government intellectual property and prevent tampering of US chip designs by external third parties.