NSF:EAGER: 2D Layered Heterostructure based Tunnel Field-Effect Transistors (TFETs) and Circuits

全球半导体/电子工业正面临着一个根本性的挑战，其形式是由互补金属氧化物半导体（CMOS）开关引起的功率和能量消耗的增加，CMOS开关在过去四十年中一直是电子工业的主力。带-带隧穿场效应晶体管（TFTs）被认为是最有前途的后CMOS开关，因为它们提供突变开关特性，从而实现超小的电源电压和开关能量，而不损害通-断开关电流比，这在常规CMOS器件中是无法实现的。然而，尽管在世界范围内做出了重大努力，但是已经发现使用诸如硅、锗或III-V半导体的常规块体材料来设计工作TFET极具挑战性，这是由于许多限制，包括它们不能减薄到低于某个临界值（这对于增加用这些材料设计的晶体管的能量效率是必不可少的），而不损失基本特性，以及由于存在由存在于所有这些共价键合材料的表面处的固有悬挂键引起的大密度界面陷阱。2-三维（2D）层状材料是原子级薄的并且具有原始表面，并且因此可以克服块体材料的限制。该项目的主要目标是探索使用二硫化钼等2D材料的可行性，以构建能够满足半导体行业性能要求的TFET，从而取代CMOS作为下一代超低功耗和节能电子开关。这种晶体管可能会彻底改变全球电子和信息技术（IT）行业，并为计算、传感和影响我们生活、工作和娱乐方式的许多其他领域带来变革性变化。小（在室温下为60 mV/decade）亚阈值摆幅（SS），因此能够实现超小电源电压和开关能量，而不会损害在常规CMOS器件中无法实现的ON-OFF电流比。然而，已经发现在块体材料平台上恢复预期的TFET性能极具挑战性，这是由于1）低效的栅极控制导致大的隧道势垒宽度和低的导通电流; 2）大的带隙导致高的隧道势垒和低的导通电流; 3）界面陷阱引起的漏电流导致大的SS。将新兴的2D材料用于TFET应用可以潜在地克服这些问题，因为2D材料具有1）相当大的带隙和带对准，其允许交错或甚至断隙型异质结设计和降低隧道势垒高度，2）超薄主体，其提供优异的栅极控制并因此降低隧道势垒宽度，以及3）原始表面，其极大地抑制陷阱产生。因此，本项目的目标是探索（理论和实验）基于TFF 10的2D材料。 更具体地说，我们建议采用二维异质结构材料平台来设计和制造所提出的TFET器件，这与文献中报道的所有以前的努力完全不同。该项目预计将对半导体和IT行业产生广泛影响。拟议研究的更广泛影响也得到了广泛认可，特别是考虑到目前全球范围内正在采用的3D集成技术，其中超低泄漏和相对温度不敏感的TFTs的最终集成可用于构建下一代高性能和超低功耗集成电路，以支持物联网，社交媒体，整个计划还将研究与各级教育联系起来。

The global semiconductor/electronics industry is confronting a fundamental challenge in the form of increasing power and energy consumption by the complementary-metal-oxide-semiconductor (CMOS) switches that have been the workhorse of the electronics industry for over four decades. Band-to-band tunneling field-effect transistors (TFETs) are considered the most promising post-CMOS switches, since they provide abrupt switching characteristics, and thereby enable ultra-small supply voltage and switching energy without compromising the ON-OFF switching current ratio, which is un-achievable in conventional CMOS devices. However, in spite of major efforts around the world, it has been found extremely challenging to design a working TFET using conventional bulk materials such as silicon, germanium or III-V semiconductors, due to a number of limitations including their inability to be thinned down below some critical value (that is essential for increasing the energy-efficiency of transistors designed with those materials), without loss of essential properties, as well as due to the existence of large density of interface traps arising from the inherent dangling bonds that exist at the surfaces of all such covalently bonded materials. 2-dimensional (2D) layered materials are atomically-thin and have pristine surfaces, and can therefore overcome the limitations of bulk materials. The main goal of this project is to explore the feasibility of using such 2D materials such as molybdenum disulphide, to build a TFET that can meet the performance requirements of the semiconductor industry and thereby replace the CMOS as the next-generation ultra-low power and energy-efficient electronic switch. Such a transistor can potentially revolutionize the worldwide electronics and information technology (IT) industries and bring transformative changes to computing, sensing and many other areas that affect the way we live, work and play.Tunneling field-effect Transistors (TFETs) are considered the most promising post-CMOS switches, since they provide abrupt switching characteristics, i.e., small (60 mV/decade at room temperature) sub-threshold swing (SS), and hence enable ultra-small supply voltage and switching energy without compromising ON-OFF current ratio, which is un-achievable in conventional CMOS devices . However, it has been found extremely challenging to recover the expected TFET performance on bulk material platform, which results from 1) inefficient gate control leading to large tunnel barrier width and low ON-current; 2) large band gap leading to high tunnel barrier and low ON-current; 3) interface trap induced leakage current leading to large SS. Utilizing the emerging 2D materials for TFET application can potentially overcome these issues, because 2D materials have 1) sizable band gap and band alignment that allow staggered- or even broken-gap type heterojunction design and lowering of tunnel barrier height, 2) ultra-thin body that provides excellent gate control and hence lowers tunnel barrier width and 3) pristine surface that greatly suppresses the trap generation. Therefore, the goal of this project is to explore (both theoretically and via experiments) 2D materials based TFETs. More specifically, we propose to employ a 2D heterostructure material platform to design and fabricate the proposed TFET device, which is radically different from all previous efforts reported in literature. This project is expected to have wide implications for the semiconductor and IT industries. Broader impact of the proposed research is also well recognized, particularly in the light of 3D integration technology now being employed worldwide, where eventual integration of ultra-low leakage and relatively temperature insensitive TFETs could be exploited to build next-generation high-performance and ultra-low power integrated circuits to support Big Data applications such as Internet of Things, social media, etc. The overall program also ties research to education at all levels.