SHF: Small: Research on Standard Cell Layout to Facilitate the VLSI Technology Scaling

物理布局在VLSI工艺节点的扩展中起着至关重要的作用。随着整个VLSI行业努力维持技术规模，范式正在从几何规模转向设计技术共同优化，并很快转向系统技术共同优化。范式的转变需要物理布局技术的进步，以解决与保持技术规模相关的新问题。该项目致力于从分析、综合和优化方面推进标准单元布局，以满足设计技术和系统技术共同优化的需求。目标是促进VLSI技术节点的扩展。该方法是在物理布局领域进行系统和设计的联合优化。这一结果将使包括消费者、市场和研发在内的整个VLSI生态系统受益。该项目正在为不同的研究生和本科生群体提供建议，包括少数民族、女性学生和处于不利条件下的学生。技术规模的研究集中在四个方面。(1)布线分析和不可布线案例诊断：分析VLSI的可布线性，诊断不可布线案例的原因，以适应日益复杂的条件设计规则。(2)图书馆单元布局综合：实现了图书馆标准单元布局的自动化，便于技术推广。(3)节距调整的设计和系统技术协同优化：该研究促进了设计和系统技术的节距调整协同优化。(4)CMOS技术的扩展和超越：探索研究3D器件、新材料和新颖的架构。项目成果包括VLSI物理布局的先进方法、理论和算法，以及一套布局工具的软件包。通过与研究实验室和技术公司的合作，这一结果将被用于超大规模集成电路的生产。这一奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

Physical layout plays an essential role in the scaling of VLSI technology nodes. As the whole VLSI industry tries to sustain technology scaling, the paradigm is shifting from geometric scaling to design technology co-optimization, and soon to system technology co-optimization. The paradigm shifts require the advancement of physical-layout techniques to tackle the new problems related to sustaining the scaling of the technology. The project works on the advancement of standard cell layout in terms of analysis, synthesis, and optimization to embrace the demand of the design technology and system technology co-optimization. The objectives are to facilitate the scaling of VLSI technology nodes. The approach is to perform system and design co-optimization in the domain of physical layout. The outcome would benefit the whole VLSI ecosystem including consumers, markets, and research and development. The project is facilitating the advising of a diverse group of graduate and undergraduate students including minority, female students, and students under adverse circumstances.The research of technology scaling is focusing on four thrusts. (1) Routing analysis and unrouteable case diagnosis: The study analyzes the VLSI routeability and diagnoses the cause of the unrouteable cases to embrace the increasing complexity of the conditional design rules. (2) Library cell layout synthesis: The research automates the library standard cell layout to facilitate the technology scaling. (3) Design and system technology co-optimization with pitch scaling: The research facilitates design and system technology co-optimization with pitch scaling. (4) Extension of CMOS technologies and beyond: The exploration studies 3D devices, new materials, and novel architectures. The project outcomes include advanced methodology, theory, and algorithms for VLSI physical layout, and software packages for a suite of layout tools. The results are being disseminated for VLSI production via collaboration with research laboratories and technology companies.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.