FET:Small: An Integrated Unipolar-0.5T0.5R RRAM Crossbar Array for Neuromorphic Computing

与传统计算技术相比，人类大脑的处理能力是无与伦比的，特别是对于以模式识别为目标的应用程序，并且需要专用硬件来模拟。神经形态（NM）计算硬件旨在通过将记忆中心和处理中心放在一起（内存中的计算）来模拟人脑的这些神经结构方面，它可以在能量尺度上提供处理和计算，比传统的冯-诺伊曼架构（在传统的冯-诺伊曼架构中，数据在单独的存储和处理元素之间传输）效率高几个数量级。因此，纳米计算可以为各种实际应用实现显著的计算进步。存储器中的计算硬件通常使用阻性随机存取存储器（RRAM）设备的横杆阵列布局来实现，其中每个存储器设备与控制晶体管串联连接，通常称为一晶体管一电阻（1T1R）单元格式。虽然这种格式保证了存储设备可靠高效地工作，但它增加了设备数量和电路面积。PI最近展示了一种新颖的“0.5T0.5R”存储单元架构，其中通过明智地使用二维（2D）材料，将控制器件（晶体管）和存储元件（RRAM）集成到单个混合器件中，从而在缩放、密度和器件/电路性能方面取得了实质性的改进。这个为期三年的项目包括设计、制造和表征这些器件的横条阵列，以实现内存中的计算硬件，从而实现大规模纳米计算电路的演示。纳米计算的应用空间以机器学习和模式识别为目标，可以用于众多现实世界的应用，而不仅仅局限于自动驾驶汽车和大数据，从而实现更广泛的科学影响。此外，纳米和内存计算范式在能效方面的显著改进将使其能够大规模部署，并使计算硬件能够跟上数据密集型应用的快速增长，尽管CMOS技术的规模限制。因此，该项目预计将对半导体和电子工业产生广泛的影响。此外，民意调查将利用各种完善的教育平台，传播研究成果，并向广大用户提供。整个项目还将研究与包括K-12、本科生、研究生和少数族裔在内的各级教育联系起来，部分通过参与由教育专业人士设计的项目，此外还将重点放在招收和留住纳米科学和工程领域代表性不足的群体上。该项目涉及新型节能神经形态/内存计算电路的概念化，设计优化和硬件演示，该电路由新型0.5T0.5R存储器件的创新大规模交叉棒阵列实现。实验工作正在密切建模和仿真支持下进行，以优化设备和阵列设计。更具体地说，在数值模拟和从头算模拟的帮助下，紧凑模型的开发有助于设备优化和开发神经学习算法，随后将在交叉杆阵列中实施，正在同步进行。该研究项目的跨学科性质，涵盖了基础的二维材料科学、器件设计和纳米制造技术，以及理论模拟和系统架构设计，确保了所提出的研究思路是可行的，并量身定制，以提供最佳的神经学习和推理目标。提出了对最近展示的纳米计算设备的重大改进，采用大面积二维材料合成技术，并配置混合设备，以提供进一步的可扩展性和易于节能寻址阵列元素。最后，演示了与模式识别、网络安全和实现物理不可克隆功能的实际应用相关的硬件神经任务。该项目的成功完成旨在推动革命性的新型纳米计算系统的发展，有效地模拟生物信息处理。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The processing capabilities of the human brain are unparalleled compared to what is achievable with conventional computing techniques, particularly for applications targeted toward pattern recognition, and needs dedicated hardware to be emulated. Neuromorphic (NM) computing hardware, which aims to mimic these neuro-architectural aspects of the human brain by having the memory- and processing-centers co-located (compute-in-memory), can deliver processing and computations on an energy scale that is orders of magnitude more efficient than the conventional von-Neumann architecture where data are transferred between separate memory and processing elements. Therefore, NM computing can enable significant computational advances for a variety of real-world applications. The compute-in-memory hardware is typically implemented using a crossbar array layout of resistive random-access memory (RRAM) devices, where each memory device is connected in series with a control transistor, in what is commonly referred to as a one-transistor one-resistor (1T1R) cell format. Although this format ensures the memory devices work reliably and efficiently, it increases the device count and circuit area. The PI has recently demonstrated a novel "0.5T0.5R" memory cell architecture where a control device - a transistor - and a memory element - a RRAM - are integrated into a single hybrid device by judicious use of two-dimensional (2D) materials with resulting substantial improvements in the scaling, density, and device/circuit performance. The three-year project involves the design, fabrication, and characterization of crossbar arrays of these devices to implement compute-in-memory hardware, thereby enabling demonstration of large-scale NM computing circuits. The application space of NM computing is targeted towards both machine learning and pattern recognition and can be used in a multitude of real-world applications not limited to self-driving cars and big data, thereby enabling a much broader scientific impact. Moreover, significant improvements in the energy-efficiency of NM and in-memory computing paradigms will enable their wide-scale deployment and enable computing hardware to keep pace with the rapid growth in data intensive applications in spite of CMOS technology scaling limitations. Thus, the project is expected to have wide implications for the semiconductor and electronics industries. Moreover, the PI will use various well established educational platforms to disseminate the research results and to make them available to a wide range of users. The overall project also ties research to education at all levels involving K-12, undergraduates, graduates, and minorities, partly via participation in programs designed by education professionals, besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.This project involves the conceptualization, design optimization, and hardware demonstration of novel and energy-efficient neuromorphic/in-memory computing circuits enabled by innovative large-scale crossbar array implementation of a novel 0.5T0.5R memory device. Experimental work is being carried out with close modeling and simulation support to optimize the device and array design. More specifically, development of compact models with the aid of numerical and ab-initio simulations to help in device optimization and developing neural learning algorithms, to be subsequently implemented in the crossbar array, is being carried out in tandem. The interdisciplinary nature of the research project, spanning fundamental 2D materials science, device design, and nano-fabrication techniques, as well as theoretical simulations and system architecture design, ensures that the proposed research ideas are feasible and tailored to deliver optimal neural learning and inference objectives. Significant improvements over recently demonstrated NM computing devices are proposed, employing large-area 2D materials synthesis techniques and configuring the hybrid device to provide further scalability and ease of energy-efficiently addressing array elements. Finally, hardware neural tasks pertaining to real-world applications of pattern recognition, cybersecurity, and implementing physically unclonable functions are being demonstrated. The successful completion of this project is intended to advance the development of a revolutionary new class of NM computing systems that efficiently emulate biological information processing.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.