Simultaneous Circuit and Layout Design Method for Analog LSIs under Performance Constraints
Simultaneous Circuit and Layout Design Method for Analog LSIs under Performance Constraints
批准号:
06680317
负责人:
ONODERA Hidetoshi
金额:
$1.41万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (C)
财政年份:
1994
资助国家:
日本
项目状态:
已结题
起止时间:
1994 至 1995
中文摘要
我们开发了一种有效的模拟lsi设计方法,该方法可以在明确考虑性能约束的情况下同时进行电路和布局设计。该方法通过三个关键技术实现;用于布局循环的符号布局技术、性能驱动的自动布局技术、基于存储设计程序的性能优化技术。我们的成就总结如下。符号布局技术在布局循环中的发展我们开发了一种符号布局技术,可以在不违反设计规则的情况下更新器件形状。当器件具有多种形状可能性时,该方法可以进一步优化器件形状,从而使总体布局空间最小化。这种技术使我们能够回收以前设计的布局,以适应新的性能规范。性能驱动布局方法的开发。在这个项目中,我们设计了一个性能驱动的全局路由方法。该方法同时处理每个路由通道中的所有网络,从而消除了网络排序问题,找到了全局最优的路由路径。“路由可能性”的概念和电阻器阵列模型可以同时考虑。利用存储设计程序的性能优化技术的发展设计参数根据从设计人员的设计过程中获得的设计程序进行优化。为了描述可信度较低的设计过程,引入了一个新的设计变量“不确定性参数”。当优化过程失败时,系统自动修改不确定性参数,使设计过程继续进行。
英文摘要
We have developed an efficient design method for analog LSIs which performs simultaneous circuit and layout design with explicit consideration of performance constraints. The method is realized by three key technologies ; symbolic layout technique for layout recycling, performance driven automatic layout, and performance optimization technique according to stored design procedures.Our achievements are summarized as follows.1. Development of symbolic layout technique for layout recyclingWe have developed a symbolic layout technique that can update device shapes without design rule violation. The method can further optimize device shapes when they have multiple shape possibilities, so that overall layout space is minimized. This technique enables us to recycle previously designed layout for accommodating new performance specifications.2. Development of performance driven layout methods.In this project, we have devised a performance driven global routing method. The method treats all the nets simultaneously in every routing channel so that net ordering problem can be eliminated and globally optimized routing paths can be found. A concept of "routing possibility" and a resistor array model enable the simultaneous consideration.3. Development of a performance optimization technique which utilizes stored design procedures Design parameters are optimized according to design procedures which are acquired from a design process of a designer. A new design variable called an "uncertainty parameter" is introduced in order to describe a design procedure with less confidence. In case the optimization process fails, the system automatically modifies the uncertainty parameter so that the design process can continue.
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H.Onodera: "Development of Module Generators from Extracted Design Procedures" IEICE Trans. Fundamentals. Vol.E78-A. 160-168 (1995)
H.Onodera:“从提取的设计程序开发模块生成器”IEICE Trans。
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H. Onodera: "Compaction with Shape Optimization and its Application to Layout Recycling" IEICE Trans. Fundamentals. E78-A. 169-176 (1995)
H. Onodera:“形状优化压实及其在布局回收中的应用”IEICE Trans。
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H.Onodera: "Global Routing Algorithm for Analog Circuits Using a Resistor Array Model" Proc.IEEE ISCAS. (to appear). (1996)
H.Onodera:“使用电阻阵列模型的模拟电路全局路由算法”Proc.IEEE ISCAS。
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H. Onodera: "Grobal Routing Algorithm for Analog Circuits Using a Resistor Array Model" Proc. IEEE ISCAS発表予定. (1996)
H. Onodera:“使用电阻阵列模型的模拟电路的全局路由算法”Proc. IEEE ISCAS (1996)。
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作者:
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通讯作者:
H.Onodera: "Compaction with Shape Optimization and its Application to Layout Recycling" IEICE Trans. Fundamentals. Vol.E78-A. 169-176 (1995)
H.Onodera:“形状优化压实及其在布局回收中的应用”IEICE Trans。
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共 7 条
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Statistical modeling method for scaled MOSFET
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负责人:ONODERA Hidetoshi
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依托单位:
海外基金