High-Performance Processor Design for Image Processing

为了探索JPEG2000编码器的体系结构，提出了一种新的设计方法。通过使用该框架，设计人员可以参考JPEG2000编码器的规范实现各种类型的JPEG2000编码器，即图像分辨率、性能要求、功耗、制造工艺、芯片尺寸限制。为了更好地利用JPEG2000算法的可扩展性，JPEG2000编码的各个过程都在该框架中有选择地实现，包括软件实现、用户自定义指令加速的软件实现和专用硬件实现。为了体现这种即插即用的特点，每个硬件模块都被设计成具有一个通用的基于SRAM的接口，只需设计接口转换器就可以支持各种总线体系结构。因此，我们的框架使得JPEG2000编码系统的设计比传统的繁琐的每个程序的手工设计任务要容易得多，传统的手工设计任务将以软件或硬件的形式实现。在该框架中设计了专用的硬件模块和软件加速，并制作了大规模集成电路来演示通过使用该框架设计的系统实现。

A novel design famework is proposed for exploring JPEG2000 encoder architecture. Through the use of this framework, a designer can implement various types of JPEG2000 encoders referring to its specification, i.e. image resolution, performance requirements, power consumption, fabrication technology, chip size limitation. In order to utilize the scalablility of JPEG2000 algorithm aggressively, each procedure of JPEG2000 encoding is selectively implemented in this framework among those by software, software accelerated with user-defined instructions, or dedicated hardware. To embody such a Plug-and-Play like feature, each hardware module is designed to have a generic SRAM-based interface which can support various bus architectures by only designing interface converters. Therefore, our framework makes it much easier to design a JPEG2000 encoding system than conventional tedious manual design tasks of each procedure, which would be implemented as software or hardware. Dedicated hardware modules as well as software acceleration are devised to be used in the framework, and an LSI is fabricated to exemplify the system implementation designed through the use of our framework.