VLSI-Based Robot Electronics System

在机器人的应用中，需要对环境的变化立即做出反应，并根据识别结果进行移动。在环境识别和运动之间需要一系列由多种加工组成的链条。在这种情况下，有必要最小化每个处理模块的绝对延迟时间，因此减少延迟在机器人专用VLSI处理器的设计中非常重要。本研究正是为此目的而进行的，主要研究结果总结如下：1.研究结果：有效的硬件算法为了使绝对延迟时间最小化，需要一种计算复杂度较低的算法。用CMOS大规模集成电路实现的坐标变换处理器就是一个典型的例子。有效地利用二维坐标旋转作为基本操作，使处理速度比传统方法快20倍左右。高度并行的架构使用并行性是另一种减少延迟时间的有效方法。在提出的体系结构中，并行处理元件oT子处理器通过互连网络连接，以便每个数据输出以最小的延迟立即传输。本文还讨论了数字伺服系统的矩阵运算处理器、逆动力学处理器、基于链码匹配的图像识别处理器和避障处理器等应用。针对硬件高度并行问题，提出了离散时间神经网络。每个单元的函数都是一个乘加运算，因此对于评价函数的最小化等优化问题总是能得到最优解。

In robot applications, it is necessary to respond immediately to the change of environment and to move according to the recognized results. A series of chains consisting of many kinds of processing is required between the environment recognition and the movement. In this case, it is necessary to minimize the absolute delay time in each processing module, so that the reduction of latency is very important in the design of VLSI processors for robotics. This research is dedicated for the above purpose, and the main results obtained are summarized as follows:1.Effective Hardware Algorithm To minimize the absolute delay time an algorithm with less computational complexity is desirable. A typical example is the coordinate transformation processor that has been implemented with CMOS LSI. Two-dimensional coordinate rotation is effectively used as a basic operation, which makes the processing speed about 20 times faster than the conventional approach.2.Highly Parallel architecture The use of parallelism is another effective approach to reduce the delay time. In the proposed architecture, the parallel processing elements oT subprocessors are connected through an interconnection network so that each data output is transferred immediately with minimum latency. The applications are also considered such as a matrix operation processor for digital servoing, an inverse dynamics processor, an image recognition processor based on chain-code matching and an obstacle avoidance processor.3.Neural Network for Optimum Solution Discrete-time neural network for highly parallel hardware is proposed. The function of each cell is a multiply-add operation, so that optimum solutions are always obtained for the optimization problems such as the minimization of an evaluation function.