Implementation of an Ultra-Higyly Parallel Residue Arithemtic Integrated Circuit Based on Multiple-Vlaued Logic and its Evaluation

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This research discusses the implementation of a new residue arithmetic integrated circuit based on multiple-valued coding and multiple-valued bidirectional current-mode MOS technology. A new multiple-valued coded residue digit representation is introduced based on the pseudo-primitive root. With this coding, mod m multiplication and mod m addition can be executed using only shift and radix-5 signed-digit arithmetic operations, respectively. Furthermore, mod m multiplication by a constant coefficient can be performed simply by exchanging wire connections.Multiple-valued bidirectional current-mode MOS technology is employed to implement the residue arithmetic circuit. In order to confirm the principle operations, the mod 7 three-operand multiply adder composed of 190 transistors has been designed and fabricated in 10-um CMOS design rule. The arithmetic circuit has a regular array structure which offers the potential for compact VLSI implementation.Although residue arithmetic operations are restricted on integer arithmetic, the above high performance can hardly be achieved thorough the use of conventional binary arithmetic circuit. This highly parallel residue arithmetic chip will be of great use in many real-time applications such as robot systems.