Research on Wafer Scale Integrated Computer

自从集成电路被发明以来，在一个芯片上集成更多的电路一直是研究和设计人员所面临的挑战。圆片级集成（WaferScaleIntegration，WSI）技术是发展大规模并行系统的重要技术之一，可以满足不断增长的计算能力需求，本研究旨在研究一种新型的圆片级计算机体系结构。我们已经提出了混合脉动排序，这是适合WSI实现。该混合分拣机具有分层冗余网络，是一种强大的容错体系结构。我们还提出了一种可重构的网状互连处理阵列的架构。我们提出的WSI阵列处理器体系结构在提高可靠性的同时也提高了成品率。立方连通环是多处理机系统中一种很有前途的网络拓扑结构。我们的处理元件放置方案比其他方案具有更高的良率。WSI系统的测试和可测性仍然是一个有待解决的问题。

Since the integarted circuit was invented, researches and designers have been challenging to get much more circuits on a chip. Wafer Scale Integration(WSI)is one of promising technologies for developing massively parallel systems which satisfy the continuous increasing demand for computer power.The aim of this research is to study a novel architecture of Wafer Scale Computer. We already proposed hybrid systolic sorters which are suitable for WSI implementation. The hybrid sorter has a hierarchical redundancy network and is powerful architecture for fault tolerance. We also proposed a reconfigurable architecture for mesh-interconnection processing arrays. Our WSI architecture of array processors achieves both higher reliability and higher production yield.We have studied on WSI architectures of cube-connected cycle multiprocessor. Cube-connected cycle is one of promising network topologies for multiprocessor systems. Our placement scheme of processing elements performs higher yield than other schemes. Testing and testability in WSI systems is still remained problems.