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Study on Post-Binary ULSI Sstems

Study on Post-Binary ULSI Sstems
后二元ULSI系统研究
批准号:
04044024
负责人:
KAMEYAMA Michitaka
金额:
$2.18万
依托单位国家:
日本
项目类别:
Grant-in-Aid for international Scientific Research
财政年份:
1992
资助国家:
日本
项目状态:
已结题
起止时间:
1992 至 1993

项目摘要

项目成果

KAMEYAMA Michitaka的其他基金

相关文献

中文摘要
翻译
目前的二值VLSI系统将面临许多严重的问题,在最终精细的几何特征尺寸。其中包括:(1)互连延迟是深亚微米集成电路性能的突出限制。(2)对于低电压操作,需要降低芯片内部的噪声。(3)并行处理性能受到处理单元之间数据通信的限制。(4)在逻辑设计、测试、电路设计和物理设计等各个层面上,大规模设计是必不可少的。(5)微电子器件中会产生隧道效应和量子效应等新现象。多值数字处理及其集成有望成为解决上述问题的最有效方案之一。这项研究的目的是展示多值集成电路a…的理论、新发展和技术更多和他们的应用。特别是,在智能集成系统应用中,功能模块间的全局通信延迟时间是决定ULSI处理器整体性能的最重要因素之一。多值数字处理技术在深亚微米几何结构中具有几个具体的优势。它们分为器件和电路层、算术逻辑算法层和系统应用层。在器件和电路层面,我们已经证明了基于器件模型的电子学对于激活适合于多值运算的器件发展的新方向变得非常重要。在算法级,我们提出了一种基于线性概念的高度并行运算电路的新设计方法。在系统应用级,我们设计了一种新型的空间并行结构的多值ULSI数字控制处理器。此外,我们还提出了一种适用于智能集成系统的通用超级芯片,具有非常灵活的网络结构。较少
英文摘要
The present binary VLSI systems will be confronted with many serious problems in an ultimately fine geometry feature size. Some of them are listed below :(1) Interconnection delay is prominent limit on the performance in the deep submicron integrated circuits.(2) For low-voltage operations, noises caused inside a chip should be reduced.(3) Parallel procesing performance is limited by data communications between processing elements.(4) Large scale design is essential at various levels such as logic design, test, circuit design and physical design.(5) New phenomena such as tunnneling and quantum effects will be caused in microelectronics devices, which is usually assumed to be inconvenient effects for binary digital operations.Multiple-valued digital processing and its integration are expected to be one of the most effective solutions for the above problems. The objective of this research is to demonstrate theories, new developments and techniques in multiple-valued integrated circuits a … More nd their applications. Especially, the delay time due to global communications between functional modules is one of the most important factors to determine the total performance In ULSI Processors for the applications of intelligent integrated systems.Several concrete advantages of multiple-valued digital procssing technology have been established in deep submicron geometry. They are classified to the device and circuit level, the arithmetic and logic algortihm level, and the system application level. In the device and circuit level, we have demonstrated that the new area called device-model based electronics becomes very important to activate the new direction of the device development suitable for multiple-valued operations. In the alogorithm level, we have proposed a new design method for highly parallel operation circuits based on a linear concept. In the system application level, we have designed a new multiple-valued ULSI processor for digital control with spatially parallel structure. Further, we have proposed a universal super chip for intelligent integrated systems with very flexible network structure. Less
期刊论文(15)
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会议论文
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通讯作者:
矢部 義一: "共鳴トンネルダイオードモデルに基づく3値Tゲートの構成" 平成4年度電気関係学会東北支部連合大会. 35 (1992)
Yoshikazu Yabe:“基于谐振隧道二极管模型的三级 T 门的配置”1992 日本电气工程师联合会东北分会 35 (1992)。
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K.SHIMABUKURO: "Design of a Multiple-Valued VLSI Processor for Digital Control" IEICE Trasactions on Information & Systems. E75-D. 709-717 (1992)
K.SHIMABUKURO:“用于数字控制的多值 VLSI 处理器的设计”IEICE Trasactions on Information
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Makoto Honda: "Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation" Trans.IEICE. E76-C. 455-462 (1993)
Makoto Honda:“基于残差算法的多值VLSI图像处理器及其评估”Trans.IEICE。
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共 13 条
    Multiple-Valued Reconfigurable VLSI Based on Adaptively Autonomous Operation
    • 批准号:
      23656230
    • 项目类别:
      Grant-in-Aid for Challenging Exploratory Research
    • 资助金额:
      $2.41万
    • 财政年份:
      2011
    • 负责人:
      KAMEYAMA Michitaka
    • 依托单位:
    Optimal VLSI Design for a Highly-Safe Intelligent Vehicle Based on a System Integration Theory
    • 批准号:
      17300009
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $8.58万
    • 财政年份:
      2005
    • 负责人:
      KAMEYAMA Michitaka
    • 依托单位:
    Development of VLSI Processor Chip Family for Highly-Safe Intelligent Vehicles Based on Optimal Design Mythologies
    • 批准号:
      12555119
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $4.61万
    • 财政年份:
      2000
    • 负责人:
      KAMEYAMA Michitaka
    • 依托单位:
    Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications
    • 批准号:
      09558025
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $5.38万
    • 财政年份:
      1997
    • 负责人:
      KAMEYAMA Michitaka
    • 依托单位: