Study on Multiple-Valued VLSI Processors for a Highly Safe Intelligent Vehicle

对于下一代超级芯片，不仅计算机世界的应用程序，而且现实世界的应用程序都将是重要的目标。在现实世界的应用中，其他的是通过真实世界的数据流，从而通过控制动作将真实世界的环境改变为期望的状态。典型的应用是机器人、智能汽车、工厂自动化、实时仪表和控制系统等。本研究项目开发了基于新型多值集成电路的高性能VLSI处理器及其关键技术如下：(1)用于高速碰撞检测和三维仪器的VLSI处理器在车辆与障碍物的碰撞检测操作中，不仅需要进行坐标变换，而且需要进行车辆与障碍物像素的匹配运算。在所提出的用于高速冲突检测的超大规模集成电路处理器中，内容地址…引入了更多的BLE存储器来存储车辆像素信息，从而大大加快了匹配操作。由于车辆像素信息是预先确定且不变的，因此提出了一种基于只读存储器单元的高性能CAM。提出了一种基于二维向量旋转和矩阵乘法的高速坐标变换的并行流水线结构；另一方面，提出了一种用于高速三维仪器的高性能VLSI结构和高效的存储器访问方案。由于候选块中的像素重叠，这些像素值由处理元件(PE)的2-D阵列重复使用。通过使用2-D PE阵列，由于图像块是像素值的2-D阵列，因此只需要本地通信。此外，还提出了一种新的存储器交织技术来并发访问帧存储器。(2)低功耗电流模式多值集成电路提出了一种新的电流源控制技术，用于在低电源电压下设计低功耗高速多值电流模式集成电路。使用具有一对双轨互补输入的差分逻辑电路(DLC)使输入信号-电压摆幅较小，从而在较低的电源电压下获得高的驱动能力，同时具有较大的静态功耗。在采用开关电流控制的DLC中，由于非有源电路模块中的电流源被关断，静态功耗大大降低。在电流控制中，不需要额外的晶体管来控制电流源，因为阈值检测器中已经使用了电流控制电路。作为算术电路的典型例子，本文还设计了一种基于0.8um标准工艺的1.5V电源54*54位乘法器。在归一化功耗下，其性能大约是二进制最快乘法器的1.3倍。(3)高性能多值内容可寻址存储器及其应用提出了一种新的高密度多值内容可寻址存储器(CAM)，用于高度并行的搜索操作。多值存储数据对应于浮栅MOS晶体管的阈值电压，因此可以仅使用单个晶体管来设计单元电路。由于一字电路中的单个匹配线用于进行多输入布线和运算，因此可以同时获得多位数据之间的幅度比较结果。结果，尽管采用了单晶体管单元电路和单匹配线架构，但仅用(n+1)步就可以执行n位的一世界幅度比较，这使得CAM单元阵列的外围电路更小。此外，典型的应用表明，所提出的非易失性CAM对于高速碰撞检测和高度并行的危险检测规则匹配等实际应用是有用的硬件加速器。此外，还提出了一种新的用于高速细胞逻辑图像处理的专用4值CAM。CAM单元中的通用文字用于同时将4值输入值与各种模板模式进行比较。具有4值数据存储能力的通用文字单元电路只需几个浮栅MOS晶体管即可实现，因为单元功能是通过简单的阈值运算和逻辑值转换来执行的。结果，与相应的基于二进制CAM的实现相比，所提出的CAM阵列中的有效单元面积大大减小。较少

For next-generation super chips, not only computer-worldapplications but also real-world applications will be important targets. In the real-world applicatins, thers is data flow passing through the real world, so that the real-world environment is changed to be the desired states by control actions. The typical applications are robotics, intelligent vehicle, factory automation, real-time instrumentation and control systems, and so on. In this reaearch project high-performance VLSI processors and their key technologies based on new multiple-valued integrated circuits have been developed an follows :(1)VLSI processors for high-speed collision detection and 3-Dimensional instrumentationIn the collision-detection operation between a vehicle and obstacles, high-computational power is essentially required in not only coordinate transformation but also matching operation between vehicle and obstacle pixels. In the proposed VLSI processor for high-speed collision detection, a content-addressa … More ble memory is introduced to store vehicle pixel information, so that the matching operation is drastically accelerated. Since vehicle pixel information is predetermined and not changed, the high-performance CAM based on a ROM cell is proposed. A parallel and pipelined architecture for the high-speed coordinate transformation is also proposed based on two-dimensional vector rotations and matrix multiplications.On the other hand, a high-performance VLSI architecture with an efficient memory access scheme is proposed for high-speed 3-D instrumentation. Since pixels in candidate blocks overlap, these pixel values are used repetitively by a 2-D array of processing elements (PEs). By using the 2-D PE array, only local communications are required since the image block is a 2-D array of pixel values. Moreover, a new memory-interleave technique is also proposed to concurrently access the frame memory.(2)Low-Power Current-Mode Multiple-Valued Integrated CircuitsA new current-source control technique is proposed to design a low-power high-speed multiple-valued current-mode (MVCM) integrated circuit in a low supply voltage. The use of a defferential logic circuit (DLC) with a pair of dual-rail complementary inputs makes an input signal-voltage swing small, which results in a high driving capability at a lower supply voltage while having large static power dessipation. In the proposed DLC using switched current control, the static power dissipation is greatly reduced because current sources in non-active circuit blocks are switched off. In the current control, no additional transistors are required to control the current sources because a current-control circuit is already used in the threshold detector. As a typical example of arithmetic circuits, a new 1.5V-supply 54*54-bit multiplier based on a standard 0.8-um CMOS technology is also designed. Its performance is about ^<1.3> times faster than of a binary fastest multiplier under the normalized powerdissipation.(3)High-Performance Multiple-Valued Content-Addressable Memory and Its ApplicationA new high-density multiple-valued content-addressable memory (CAM) is proposed for highly parallel search operations. Multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. Since a single match line in a one-word circuit is used for performing a multi-input wired AND opearion, the magnitude comparison result between multi-digit data can be obtained simultaneously. As a result, a one-world magnitude comparison with n digits can be performed by just (n+1) steps in spite of a single-transistor cell circuit and single-match-line architecture, which makes the peripheral circuit of a CAM cell array small. Moreover, typical applications clearly demonstrate that theproposed non-volatile CAM is useful as a hardware accelerator for various real-world applications such as high-speed collision detection and highly parallel danger-detection rule matching.Moreover, a new special-purpose 4-valued CAM is also proposed for high-speed cellular logic image processing. A universal literal in CAM cell is used to compare a 4-valued input value with various template patterns simultaneously. The universal-literal cell circuit with 4-valued data storage capability can be implemented by just a few floating-gate MOS transistors, since the cell function is performed by simple threshold operations together with logic-value conversion. As a result, the effective cell area in the proposed CAM array is greatly reduced in comparison with that in a corresponding binary CAM-based implementation. Less