Development of ultra-high-speed LSI with gas-isolated-interconnects and Ta metal gate transistors on SOI substrate

本研究的目的是建立超高速、高集成度的千兆级集成技术，使集成电路的工作频率从目前认为的最高速度不到1ghz加速到20ghz，从而开发出理想的器件结构、工艺和材料，实现半导体集成电路的超加速和低功耗。由于闸门损耗的问题，应该需要一个金属闸门。本研究开发了以低温工艺为特征的金属栅极技术。特别是采用450℃以下的完美低温工艺，首次制成了以直接氮化硅为栅绝缘子的Ta栅FD-SOI MNSFET，亚阈值系数达到66 mV/dec的理想性能，界面性能非常好。在高栅极偏置区，MNSFET的互导比传统MOSFET高，电流驱动能力也比传统MOSFET高。Si/SiO_2 （SOI/BOX）界面的电活度缺陷对SOI器件的性能和可靠性有很大影响。本文首次对FD-SOI MOSFET的后门偏置互导特性进行了实验测量。此外，本文还推导了考虑SOI层-衬底之间电位下降的薄膜SOI MOS器件表面电位的计算公式，并阐明了与扭转现象相对应的SOI/BOX界面的陷阱能级能级和高剂量SIMOX衬底陷阱能级及其密度。随着MOS器件的小型化，为了提高其性能，必须降低电源电压。因此，降低低频噪声以提高信噪比变得十分重要。在本研究中，首次分析了部分耗尽型SOI器件的低频噪声特性，并且采用ELTRAN晶圆的SOI MOSFET的噪声谱在预结域中纯粹等效于1/f型。少

The purpose of this study is to establish ultra-high speed and high integrated giga scale integration technology that the operating frequency of integrated circuit has been accelerated up to 20 GHz though the maximum speed was so far thought less than 1 GHz in order to develop the ideal device structure, process and material to realize ultra acceleration and low electric power consumption of semiconductor integrated circuit. Because of a problem of Gate depletion, a metal gate should be needed. In this study, Ta metal gate technology characterized by the low-temperature process was developed. Especially, using perfect low-temperature processes below 450 ℃, Ta gate FD-SOI MNSFET using the direct silicon nitride as a gate insulator was made for the first time, and it was found that the sub-threshold coefficient had the ideal property of 66 mV/dec, and the interface property was very good. Furthermore, it is clarified that the mutual conductance of this MNSFET was higher than that of conv … More entional MOSFET at high gate bias region, and also the current drive capability was higher than that of conventional MOSFET.The performance and reliability of the SOI device is strongly influenced to the electric activity defect of Si/SiO_2 (SOI/BOX) interface. In this study, the back gate bias - mutual conductance property of FD-SOI MOSFET was experimentally measured for the first time. Moreover, the formula of the surface potential in the thin film SOI MOS device in consideration of the potential drop between the SOI layer - substrate was newly derived, and also the energy level of the trap level for the SOI/BOX interface corresponding to a kink phenomenon and the high dose SIMOX substrate trap level and its density were clarified.With miniaturization of a MOS device, the electric power-supply voltage must be reduced in order to improve the performance. Therefore, the reduction of the low frequency noise for improving a S/N ratio becomes very important from now on. In this research, it is clarified that the low frequency noise property of a partial depletion type SOI device was analyzed for the first time, and also the noise spectrum in SOI MOSFET adopted the ELTRAN wafer is purely equivalent to 1/f type in the pre-kink domain. Less