Silicon Resonant Tunnelling Diodes and Circuits

谐振隧穿二极管（rtd）是为数不多的量子器件技术之一，与竞争对手的器件和电路相比，其生产性能优越。所有这些电路都是III-V技术，而超过98%的微电子销售是硅器件。剑桥大学之前的工作已经证明了Si/SiGe rtd的III-V型性能。该提案是开发和演示使用Si/SiGe rtd结合应变Si mosfet的基本电路，如果这种技术要实现生产飞跃，则需要一个关键步骤。本文将研究隧道静态随机存取存储器（TSRAM）的应用。TSRAM具有使用应变si技术与未来CMOS微处理器集成的能力，因此被纳入国际半导体技术路线图（ITRS）的RTD技术。特别是TSRAM有可能在CMOS SRAM待机功耗方面提供7个数量级的改进，这是CMOS微处理器未来扩展中最重要的参数之一。我们还建议开发现有的摩尔定律、缩放和后摩尔设备的外展教学资源，以鼓励儿童进入与拟议研究相关的科学和英国半导体行业。我们提出的工作也与英国EPSRC硅期货网络（GR/T07879）提出的EPSRC硅技术的重大挑战相一致。这个特殊的提议在某种程度上跨越了所有的技术大挑战，但器件架构向临界尺寸为~ 2nm的rtd的变化与G1：使用硅基技术的新型器件和工艺最为一致。该提案将开发和验证rtd的量子器件模型（G2.2），并在纳米尺度（G3）上使用多种表征技术。RTD技术正在使用SiGe，因此我们正在解决G4：硅基技术的新材料系统。与SRAM相比，待机功耗也降低了7个数量级，这也与G7生态硅大挑战相一致，并且一项成功技术的许多潜在应用，特别是DAC和ADC电路，与G6生命硅大挑战有着密切的联系。

Resonant tunnelling diodes (RTDs) are one of the few quantum device technologies which has made production with superior performance compared to rival devices and circuits. All such circuits have been in III-V technology while over 98% of microelectronic sales are silicon devices. Previous work at Cambridge has demonstrated III-V type performance from Si/SiGe RTDs. This proposal is to develop and demonstrate basic circuits using Si/SiGe RTDs combined with strained-Si MOSFETs, a key step required if such technology is to make the leap to production. One application will be investigated as a demonstrator, that of tunnelling static random access memory (TSRAM). The TSRAM has the ability to be integrated with future CMOS microprocessors using strained-Si technology, hence the inclusion in the International Technology Roadmap for Semiconductors (ITRS) of RTD technology. In particular the TSRAM potentially offers 7 orders of magnitude improvement in CMOS SRAM standby power dissipation, now one of the most important parameters in the future scaling of CMOS microprocessors. We also propose to develop existing outreach teaching resources on Moore's law, scaling and post Moore devices to encourage children into science and the U.K. semiconductor industry linked to the proposed research.The work we propose is also aligned with the EPSRC Signposted Grand Challenges in Silicon Technology as set out by the U.K. EPSRC Silicon Futures network (GR/T07879). This particular proposal to some degree straddles all the Technology Grand Challenges but the change of device architecture to RTDs with ~2 nm critical dimensions is most strongly aligned to the G1: Novel Devices and Processes Using Silicon Based Technology. This proposal will develop and validate quantum device models of RTDs (G2.2) and use numerous characterisation techniques at the nm scale (G3). The RTD technology is using SiGe and so we are addressing G4: New Materials Systems for Silicon Based Technologies. As standby power dissipation is also reduced by 7 orders of magnitude compared to SRAM, this is also aligned with the G7 Eco-silicon Grand Challenge and the many potential applications for a successful technology especially with DAC and ADC circuits has strong associations with the G6 Silicon for Life Grand Challenge.