Higher Fidelity Etch Profiles and Reduced Charge Damage in Integrated Circuit Manufacturing by Neutralizing Charge Imbalances During Plasma Etch

点击翻译按钮获取中文摘要

0097061CollinsFor the past 20 years, conventional integrated circuit (IC) plasma etch processes have successfully employed a flux of positive ions to activate surface chemistry. As feature sizes are reduced to below 0.25 microns, spatial charge buildup on etch features already contributes to non-ideal etch profiles, limits etch feature size, and damages MOSFET gate oxide, resulting in lower chip yield. The PI seeks both a scientific understanding and a cure for this potential IC manufacturing showstopper for plasma etch of features down to 0.1 micron.The PI proposes to explore positive charge buildup neutralization via simultaneous electron irradiation of the IC during plasma etching, utilizing a CSU developed electron beam source. Proof-of-principle electron beam irradiation, described within, proves we can successfully transmit electron beams at current levels of up to ~1 mA/cm 2 through high ion density (N+ = 10 12 cm -3 ) plasmas to etching substrates. Etch profiles in preliminary experiments with and without electron irradiation are very distinct, indicating that the PO's approach of charge neutralization is a potentially effective technique.The proposed two-part research program builds on the PI's prior proof-of-principle studies. Part one involves production, transmission, and characterization of an electron beam through a reactive plasma etching environment to an etch substrate. Experimentally measured beam spectra will be compared to numerical simulations for quantification of negative charge deposited on test structures prior to the onset of proposed etch profile and charge damage studies.In part two, the PI will examine the effect of various controlled levels of electron beam irradiation on feature profiles during plasma etching, and isolate charge neutralization effects from other known contributors. Agilent Technologies Integrated Circuit Business Division will provide a variety of IC test structures with pre-etched high aspect ratio photo-resist features placed on top of dual plate capacitors to quantify both the positive and negative charge deposited. The existing Agilent Technologies database for plasma etching with ion fluxes alone will baseline his studies and provide the initial operating parameters where cumulative ion charge in microstructures is known to be deleterious.In summary,the PI's research will construct a database of charge neutralization etch conditions. Both neutralization of positive charge in micro-features to improve pattern fidelity of high aspect ratio features as well as blanket charge neutralization to reduce MOSFET gate oxide damage during plasma etch will be quantitatively explored.