Higher Fidelity Etch Profiles and Reduced Charge Damage in Integrated Circuit Manufacturing by Neutralizing Charge Imbalances During Plasma Etch

通过中和等离子蚀刻期间的电荷不平衡，提高集成电路制造中的蚀刻轮廓保真度并减少电荷损坏

• 批准号: 0097061
• 负责人: George Collins
• 金额: $ 21万
• 依托单位: Colorado State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-05-01 至 2004-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0097061&HistoricalAwards=false
• 关键词: Higher; Fidelity; Etch; Profiles; Reduced

0097061CollinsFor the past 20 years, conventional integrated circuit (IC) plasma etch processes have successfully employed a flux of positive ions to activate surface chemistry. As feature sizes are reduced to below 0.25 microns, spatial charge buildup on etch features already contributes to non-ideal etch profiles, limits etch feature size, and damages MOSFET gate oxide, resulting in lower chip yield. The PI seeks both a scientific understanding and a cure for this potential IC manufacturing showstopper for plasma etch of features down to 0.1 micron.The PI proposes to explore positive charge buildup neutralization via simultaneous electron irradiation of the IC during plasma etching, utilizing a CSU developed electron beam source. Proof-of-principle electron beam irradiation, described within, proves we can successfully transmit electron beams at current levels of up to ~1 mA/cm 2 through high ion density (N+ = 10 12 cm -3 ) plasmas to etching substrates. Etch profiles in preliminary experiments with and without electron irradiation are very distinct, indicating that the PO's approach of charge neutralization is a potentially effective technique.The proposed two-part research program builds on the PI's prior proof-of-principle studies. Part one involves production, transmission, and characterization of an electron beam through a reactive plasma etching environment to an etch substrate. Experimentally measured beam spectra will be compared to numerical simulations for quantification of negative charge deposited on test structures prior to the onset of proposed etch profile and charge damage studies.In part two, the PI will examine the effect of various controlled levels of electron beam irradiation on feature profiles during plasma etching, and isolate charge neutralization effects from other known contributors. Agilent Technologies Integrated Circuit Business Division will provide a variety of IC test structures with pre-etched high aspect ratio photo-resist features placed on top of dual plate capacitors to quantify both the positive and negative charge deposited. The existing Agilent Technologies database for plasma etching with ion fluxes alone will baseline his studies and provide the initial operating parameters where cumulative ion charge in microstructures is known to be deleterious.In summary,the PI's research will construct a database of charge neutralization etch conditions. Both neutralization of positive charge in micro-features to improve pattern fidelity of high aspect ratio features as well as blanket charge neutralization to reduce MOSFET gate oxide damage during plasma etch will be quantitatively explored.

在过去的20年里，传统的集成电路(IC)等离子体刻蚀工艺成功地使用了一种正离子通量来激活表面化学。随着特征尺寸减小到0.25微米以下，刻蚀特征上的空间电荷积累已经导致了不理想的刻蚀轮廓，限制了刻蚀特征尺寸，并损坏了MOSFET栅氧化物，导致芯片成品率较低。PI既寻求科学的理解，又寻求解决这一潜在的IC制造展示的方法，用于等离子体刻蚀小至0.1微米的特征。PI建议利用CSU开发的电子束源，通过在等离子体刻蚀过程中同时对IC进行电子辐照来探索正电荷积累中和。中描述的电子束辐照原理证明，我们可以成功地将高达~1 mA/cm2电流水平的电子束通过高离子密度(N+=10 12 cm-3)等离子体传输到刻蚀基片上。在有电子辐照和没有电子辐照的初步实验中，刻蚀轮廓非常不同，表明PO的电荷中和方法是一种潜在的有效技术。拟议的两部分研究计划建立在PI先前的原理证明研究的基础上。第一部分涉及电子束通过反应等离子刻蚀环境到刻蚀衬底的产生、传输和表征。实验测量的束流光谱将与数值模拟进行比较，以量化在建议的刻蚀轮廓和电荷损伤研究开始之前沉积在测试结构上的负电荷。在第二部分，PI将检查不同受控水平的电子束辐照对等离子体刻蚀过程中特征轮廓的影响，并将电荷中和效应与其他已知的贡献者隔离开来。安捷伦技术集成电路业务部将提供各种IC测试结构，在双板电容器上放置预刻蚀的高深宽比光致抗蚀剂特征，以量化沉积的正电荷和负电荷。仅安捷伦技术公司现有的离子熔剂等离子体蚀刻数据库就将为他的研究提供基线，并提供已知微结构中累积的离子电荷有害的初始操作参数。总而言之，PI的研究将构建电荷中和蚀刻条件的数据库。我们将定量地探讨如何中和微特征中的正电荷以提高高深宽比特征的图形保真度，以及如何通过包层电荷中和来减少等离子体刻蚀过程中MOSFET栅氧化物的损伤。