Nanoscale Si Based Crossbar Architecture for Memory and Logic Operations

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We propose to implement a scheme for reconfigurable computing using metallic nanowire crossbar arrays, in which the active component at each cross point is based on an amorphous silicon (a-Si) - crystalline silicon (c-Si) heterostructure.As the device integration level reaches the projected terasbit scale (1012 devices/cm2), novel, radical changes in device structures and architectures will be needed to facilitate the escalating demands of defect tolerance and massive interconnects associated with nanoscale devices. Reconfigurable architectures, in particular, crossbar structures in which the active components are hysteretic resistors formed at the points where two nanowire arrays crossing each other, have emerged as a leading candidate. The crossbar scheme offers inherent defect tolerant capability, as the circuit can be easily rerouted around defect components. The simple two-terminal active device structure makes it suitable for aggressive scaling, with the potential that both logic and memory functions can be integrated in the same entity. In a typical crossbar structure, arrays of metallic nanowires are used as both the interconnects and the contact leads, and self-assembled molecules are proposed as the active, hysteretic component. However, switches based on molecules suffer from serious issues such as low yield, slow switching speed and low on/off ratio, which greatly affect their application potential.In this proposal, we present an alternative, solid-state based system that precisely addresses these issues, by utilizing an a-Si/c-Si heterostructure as the active component in a metallic nanowire crossbar array. Compared to molecule based devices, the Si heterostructure devices offer comparable scalability down to nanometer scale, while exhibiting nearly ideal properties for hysteretic switching, such as high yield, fast switching speed, well-defined thresholds and high on/off ratio. Furthermore, intrinsic rectifying behavior, a property that eliminates crosstalk and is highly desirable in the crossbar scheme, can be achieved in our device structure through proper material engineering. The proposed Si heterostructure crossbar arrays will offer up to terabit-scale density in a defect tolerant, reconfigurable architecture, while being fabricated on a reliable platform that is also compatible with available Si technology. In particular, high density, non-volatile memories with integrated decoder devices that interface the nanoscale components with microscale electronics will be demonstrated. General logic applications based on the crossbar structures will also be explored, with emphasis on a hybrid crossbar/CMOS approach. The proposed work is highly interdisciplinary in nature, and requires close collaboration with chemists, materials scientists, and computer scientists. The research component of the activities described in this proposal will be closely tied to educational and other activities intended to broaden the impact of the proposed research. The research will provide educational and training opportunities for a graduate student who will be exposed to state-of-the-art experimental techniques and given a chance to present his or her results at appropriate conferences. Undergraduates will be routinely involved in the research as well. For example, first and second year undergraduates, who would not otherwise be exposed to cutting-edge research, will be directly involved through U-M's UROP program. Summer research opportunities will also be offered to undergraduates through U-M's SROP program and NSF's REU program. Furthermore, knowledge and techniques developed during research will be incorporated into the special topics course the PI is developing: Introduction to Nanoelectronics, which is offered to students in both engineering and science divisions.