Research on extremely low-power and scaled Si-based CMOS devices making the best use of SiGe and SOI

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In this study, in order to realize future low-power and high-speed CMOS devices, we have tried to apply SiGe material and SOI (Silicon-on-Insulator) structure to Si CMOS, and have investigated the device performance, analyzed the characteristics, and developed new evaluation methods of the devices.(1) It was confirmed that strained SiGe-channel pMOSFETs show twice higher transconductance compared with conventional counterparts.(2) It was shown that drain leakage current in the SiGe-channel pMOSFETs increases with the increase in the SiGe thickness over a critical value. The mechanism of the leakage current was clarified, and guidelines for the Ge fraction and the SiGe thickness were obtained.(3) 0.1-micron-gate pMOSFETs with raised source/drain structures and extremely-shallow source/drain junctions were fabricated using low-temperature doped-SiGe selective-epitaxial growth, and it was verified that the technique is effective to suppress short channel effects, and to obtain excellent drain drivability due to the low-resistance shallow source/drain structure.(4) It was clarified that low-frequency noise in the SiGe-channel pMOSFETs, which is an important factor for their analogue applications, can be lower than that in conventional Si pMOSFETs.(5) Hot-carrier-induced instability in Lorentzian-like excess low-frequency noise in floating-body SOI MOSFETs was found for the first time, and its mechanism was clarified.(6) An experimental method to directly measure the interface-trap-density in the SiGe/Si heterostructure, which is introduced to the channel region in the SiGe-channel MOSFETs, was established by using the charge pumping technique. The method is effective to investigate the relationship between the device characteristics and the electrical quality of the heterostructure interface.