权益分类	功能权益	普通用户	{{item.name}}会员
{{category.name}}	{{benefitItem.name}}

Studies on Metal/Ferroelectric/Insulator/Semiconductor (MFIS) -FET Memories Obeying The Scaling Rule

遵守比例规则的金属/铁电/绝缘体/半导体 (MFIS) -FET 存储器的研究

基本信息

批准号：
09450147
负责人：
SHOJI Shuichi
金额：
$ 10.37万
依托单位：
Waseda University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1999
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09450147/
关键词：
Ferroelectric materials Memory MFIS-FET Scaling CeOィイD22ィエD2 Self-align process High Aspect ratio 3 layers resist method 強誘電体メモリ FETメモリ微細加工チタン酸鉛 YSZ ヘテロエピタキシー SBT ヘテロエピタキシ-

项目摘要

Metal/Ferroelectric/Insulator/Semiconductor (MFIS)-FET memories have been studied. MFIS-FET memory in which the surface potential of Si is controlled by the remanent polarization of ferroelectric materials, has the significant advantages of obeying the scaling rule, high switching speed, nonvolatility, radiation tolerance and high density. The results of our work are as follows.(1) Fabrication of the Metal/Ferroelectric/Insulator/Semiconductor (MFIS) structuresTo obtain a good interface which acts as the gate oxide for Metal/Ferroelectric/Semiconductor (MFS)-FETs and to obtain ferroelectric films with preferred for use as intermediate layers between the ferroelectric material and the Si sybstrate for MFIS-FETs. By using ceria-zirconia mixture (Ce・ZrOィイD22ィエD2) films on Si substrate, CeOィイD22ィエD2 can be grown epitaxially. Ce-Ce・ZrOィイD22ィエD2 films are good intermediate layers between a ferroelectric material and Si (100) for MFIS-FET. We also developed a deposition method of PLZT on CeOィ … More イD22ィエD2 buffer layer using the sol-gel method. By optimizing the annealing steps, PLZT can be also grown hetero epitaxially. On the other hand, MSIF structure having the SrBiィイD22ィエD2TaィイD22ィエD2OィイD29ィエD2 (SBT) as a poly crystalline ferroelectric material are also fabricated using SiON as a intermediate layer, which shows good C-V characteristics.(2) Fabrication of the MFIS-FET with self-alignment techniqueTo obtain microfabrication of MFIS-FETs with good high frequency characteristics, self-alignment technique was developed. A Pt, SBT and SiON were used as the gate metal, the ferroelectric material and the buffer layer. These three layers are patterned by the plasma dry etching with a single photoresist mask. The W/L of the MSIF-FET was 700/150 μm. To reduce the gate dimensions, reactive ion etching (RIE) is requested for the etching.(3) Studies on microfabrication methods of MFIS-FETsIn order to fabricate 1μm or smaller than 1 μm gate MFIS-FETs with simple self-alignment process, a high aspect ratio mask layer is needed. UV photoresist of EPON SU-8 was utilized for this purpose. Fine resolution of 1.5 μm with aspect ratio of 8 was obtained. We also studied three layer resist method using EB direct writing and RIE method. High resolution of about 0.5μm with aspect ratio of about 6.5 was realized. Less

已经研究了金属/铁电/绝缘体/半导体（MFIS）-FET存储器。MFIS-FET存储器利用铁电材料的剩余极化来控制Si的表面电位，具有遵守比例尺定律、开关速度快、非易失性、耐辐射性和高密度等显着优点。我们的工作结果如下。(1)金属/铁电/绝缘体/半导体（MFIS）结构的制备为了获得用作金属/铁电/半导体（MFS）-FET的栅极氧化物的良好界面，并且获得优选用作MFIS-FET的铁电材料和Si衬底之间的中间层的铁电膜。在Si衬底上用CeO 2-ZrO 2混合物（Ce·ZrO_2D_2）薄膜外延生长CeO_2D_2_2D_2。Ce-Ce·ZrO_xD_22薄膜是MFIS-FET中铁电材料和Si（100）之间的良好中间层。我们还开发了一种在CeO陶瓷上沉积PLZT的方法 ...更多信息用溶胶-凝胶法制备了一种新型的D2缓冲层。通过优化退火步骤，PLZT也可以异质外延生长。另一方面，还使用锡永作为中间层来制造具有SrBi掺杂D22掺杂D2 Ta掺杂D22掺杂D2 O掺杂D29掺杂D2（SBT）作为多晶铁电材料的MSIF结构，其显示出良好的C-V特性。(2)采用自对准技术制作MFIS-FET为了获得具有良好高频特性的MFIS-FET的微细加工，发展了自对准技术。Pt、SBT和锡永被用作栅极金属、铁电材料和缓冲层。这三个层通过用单个光致抗蚀剂掩模的等离子体干法蚀刻来图案化。MSIF-FET的W/L为700/150 μm。为了减小栅极尺寸，要求使用反应离子蚀刻（RIE）进行蚀刻。(3)为了用简单的自对准工艺制作1μm或小于1 μm的栅MFIS-FET，需要一种高深宽比的掩模层。为此目的，使用EPON SU-8的UV光致抗蚀剂。分辨率为1.5 μm，纵横比为8。研究了EB直写和RIE三层抗蚀剂的制备方法。实现了约0.5μm的高分辨率和约6.5的纵横比。少