Studies on Metal/Ferroelectric/Insulator/Semiconductor (MFIS) -FET Memories Obeying The Scaling Rule

遵守比例规则的金属/铁电/绝缘体/半导体 (MFIS) -FET 存储器的研究

基本信息

批准号：
09450147
负责人：
SHOJI Shuichi
金额：
$ 10.37万
依托单位：
Waseda University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1999
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09450147/
关键词：
Ferroelectric materials Memory MFIS-FET Scaling CeOィイD22ィエD2 Self-align process High Aspect ratio 3 layers resist method 強誘電体メモリ FETメモリ微細加工チタン酸鉛 YSZ ヘテロエピタキシー SBT ヘテロエピタキシ-

项目摘要

Metal/Ferroelectric/Insulator/Semiconductor (MFIS)-FET memories have been studied. MFIS-FET memory in which the surface potential of Si is controlled by the remanent polarization of ferroelectric materials, has the significant advantages of obeying the scaling rule, high switching speed, nonvolatility, radiation tolerance and high density. The results of our work are as follows.(1) Fabrication of the Metal/Ferroelectric/Insulator/Semiconductor (MFIS) structuresTo obtain a good interface which acts as the gate oxide for Metal/Ferroelectric/Semiconductor (MFS)-FETs and to obtain ferroelectric films with preferred for use as intermediate layers between the ferroelectric material and the Si sybstrate for MFIS-FETs. By using ceria-zirconia mixture (Ce・ZrOィイD22ィエD2) films on Si substrate, CeOィイD22ィエD2 can be grown epitaxially. Ce-Ce・ZrOィイD22ィエD2 films are good intermediate layers between a ferroelectric material and Si (100) for MFIS-FET. We also developed a deposition method of PLZT on CeOィ … More イD22ィエD2 buffer layer using the sol-gel method. By optimizing the annealing steps, PLZT can be also grown hetero epitaxially. On the other hand, MSIF structure having the SrBiィイD22ィエD2TaィイD22ィエD2OィイD29ィエD2 (SBT) as a poly crystalline ferroelectric material are also fabricated using SiON as a intermediate layer, which shows good C-V characteristics.(2) Fabrication of the MFIS-FET with self-alignment techniqueTo obtain microfabrication of MFIS-FETs with good high frequency characteristics, self-alignment technique was developed. A Pt, SBT and SiON were used as the gate metal, the ferroelectric material and the buffer layer. These three layers are patterned by the plasma dry etching with a single photoresist mask. The W/L of the MSIF-FET was 700/150 μm. To reduce the gate dimensions, reactive ion etching (RIE) is requested for the etching.(3) Studies on microfabrication methods of MFIS-FETsIn order to fabricate 1μm or smaller than 1 μm gate MFIS-FETs with simple self-alignment process, a high aspect ratio mask layer is needed. UV photoresist of EPON SU-8 was utilized for this purpose. Fine resolution of 1.5 μm with aspect ratio of 8 was obtained. We also studied three layer resist method using EB direct writing and RIE method. High resolution of about 0.5μm with aspect ratio of about 6.5 was realized. Less

金属/铁电/绝缘子/半导体（MFIS） - fet记忆已经研究了。 MFIS-FET存储器在其中Si的表面电势受到铁电材料的隔离极化控制，具有遵守缩放规则，高开关速度，不易位性，辐射耐受性和高密度的显着优势。 The results of our work are as follows.(1) Fabrication of the Metal/Ferroelectric/Insulator/Semiconductor (MFIS) structuresTo obtain a good interface which acts as the gate oxide for Metal/Ferroelectric/Semiconductor (MFS)-FETs and to obtain ferroelectric films with preferred for use as intermediate layers between the ferroelectric material and the Si sybstrate for MFIS-FET。通过在SI底物上使用ceria-Zirconia混合物（Ce ・ Zroii D22E D2）膜，CEOI D22E D2可以在同在。 CE-CE ・ ZROI D22E D2膜是铁电材料和MFIS-FET的SI（100）之间的良好中层层。我们还使用SOL-GEL方法开发了一种在CEOI上的PLZT的沉积方法…更多ID22E D2缓冲层。通过优化退火步骤，PLZT也可以在外世上生长。另一方面，具有SRBII D22E D2TAYY D22E D22E D2YY D29E D2（SBT）作为多层铁电启材料的MSIF结构也使用sion作为中间层制造，这显示了良好的C-V特征。开发了自我对准技术。 PT，SBT和SION用作栅极金属，铁电材料和缓冲层。这三层是由血浆干燥蚀刻带有单个光蛋白师掩模的。 MSIF-FET的W/L为700/150μm。为了降低栅极尺寸，请求反应性离子蚀刻（RIE）进行蚀刻。（3）关于MFIS-Fetsin的微分化方法的研究，以制造具有简单的自我对齐过程的1μm或小于1μm的Gate MFIS MFIS-FETS，需要高纵横比掩模层。 EPON SU-8的紫外线光蛋白师用于此目的。获得了1.5μm的细分辨率，纵横比为8。我们还使用EB直接写作和RIE方法研究了三层抵抗方法。实现了约0.5μm的高分辨率，长宽比约为6.5。较少的