STUDIES ON QUANTUM EFFECT DEVICE MODELING BASED ON DEVICE STRUCTURE AND FUNCTIONAL CIRCUITS

基于器件结构和功能电路的量子效应器件建模研究

• 批准号: 08455167
• 负责人: TANIGUCHI Kenji
• 金额: $ 2.69万
• 依托单位: KYUSHU UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1996
• 资助国家: 日本
• 起止时间: 1996 至 1997
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-08455167/
• 关键词: QUANTUM EFFECT DEVICE; HEMT; RTD; MODELING; PLL; DEVICE SIMULATION; CELL LIBRARY; 機能回路; デバイス構造; 回路シミュレーション

IN ORDER TO ESTABLISH DESIGN METHDOLOGY OF FUNCTIONAL CIRCUITS USING QUANTUM EFFCT DEVICES SUCH AS HEMT AND RTD DEVICES,WE HAVE STUDIED QUANYUM EFFECT DEVICE MODELING FOR CIRCUIT SIMULATION BASED ON PHYSICAL STRUCTURE,AND DESIGNED HEMT CELL LIBRARY FOR TOP-DOWN LSI DESIGN.AND WE HAVE ALSO DESIGNED FUNCTIONAL CIRCUITS FOCUSED ON HIGH-SPEED PLL.THE FOLLOWING RESULTS ARE OBTAINED.1.PHYSICAL STRUCTURE BASED DEVICE MODELINGTHE DEVICE MODELING BASED ON PHYSICAL STRUCTURE PREVIOUSLY PROPOSED BY THE INVESTIGATORS ARE APPLIED TO CIRCUIT SIMULATION MODEL.THE RESULTS SHOW THAT IT IS APPLICAPABLE TO CIRCUIT SIMULATION.FOR MORE WIDE VARIETY OF DEVICE STRUCTURE,DEVICE SIMULATOR IS INTRODUCED.THE METHOD TO ESTIMATE DEVICE CHARACTERISTICS AND CIRCUIT MODEL WITH DEVICE SIMULATION IS ESTABLISHED.2.FUNCTIONAL CIRCUITS FOR PLLPRIMITIVE GATES USING RTD/HEMT STACK STRUCTURE ARE INVESTIGATED.RTD/HEMT GATES HAVE HIGHER SPEED AND LOWER POWER CONSUMPTION CHARACTERISTICS COMPARED WITH CONVENTIONAL DCFL GATES.AND A 3-MODE PLL WHICH HAS FAST PULL-IN CHARACTERISTICS IS DESIGNED IN 0.3UM HEMT TECHNOLOGY IS DESIGNED AND SIMULATED.IT IS CONFIRMED THAT THE DESIGNED PLL CAN OPERATE UP TO 2.2 GHZ AT 1V DC POWER SUPPLY.AIMING ACHIEVE HIGHER SPEED AND LOWER POWER BY HEMT DYNAMIC CIRCUITS,PRELIMINARY INVESTIGATION ARE CARRIED OUT BY CMOS TECHNOLOGY.3.TOP-DOWN DESIGN USING QUANTUM EFFECT DEVICESFOR TOP-DOWN LSI DESIGN USING HEMT DEVICE,CELL LIBRARY CORRESPONDING TO FUNCTIONAL CMOS CELL LIBRARY IS DESIGNED.THE CELL LIBRARY HAS 49 BASIC CELLS WITH 1V POWER SUPPLY VOLTAGE.USING THIS CELL LIBRARY TEST CIRCUITS ARE DESIGNED BY VERILOG-HDL AND CONFIRMED.BASIC DESIGN ENVIRONMENT COMPATIBLE WITH CONVENTIONAL CMOS TO-DOWN DESIGN IS ESTABLISHED FOR HEMT LSI.

为了建立基于HEMT和RTD等量子器件的功能器件的设计方法，我们研究了基于物理结构的量子效应器件建模方法，和用于自顶向下LSI设计的可编程HEMT单元库。我们还提供了专注于高性能的可编程功能库。1.基于物理结构的器件建模结果表明，该模型适用于器件结构的动态仿真，介绍了器件模拟器，建立了用器件模拟器估算器件特性的方法和模拟器模型。2.给出了RTD/HEMT叠层结构的半导体门的功能特性。RTD/HEMT门与传统的DCFL门相比，具有更高的速度和更低的功耗特性。3.提出了一种3-在0.3 μ mHEMT工艺中实现了具有快速拉入特性的2.2GHz锁相环，并进行了仿真验证，证实了该锁相环在1V直流电源下工作频率可达2.2GHz，为实现HEMT动态锁相环的高速、低功耗，利用CMOS工艺进行了初步研究。3.基于量子效应器件的自顶向下设计设计了一个与功能CMOS单元库相对应的单元库，该单元库包含49个基本单元，电源电压为1V，利用该单元库对测试结果进行了Verilog-HDL验证，建立了一个与传统CMOS自下而上设计兼容的HEMT LSI基本设计环境。

项目成果

YOUSUKE KUDOU: "HEMT DEVICE CHARACTERISTICS CALCULATION AND MODELING BASED ON DEVICE STRUCTURE" RESEARCH REPORTS ON ISEE,KYUSHU UNIVERSITY. (IN PRINT). 6 (1998)

YOUSUKE KUDOU：《基于器件结构的HEMT器件特性计算与建模》九州大学ISEE研究报告。

Ikuo Seki: "A Design of First-Order Delay-Line DPLL in 1.2um CMOS Technology" Research Reports on ISEE,Kyushu University. 1・1. 45-50 (1996)

Ikuo Seki：“1.2um CMOS 技术中的一阶延迟线 DPLL 的设计”ISEE 的研究报告，九州大学 1・1（1996 年）。

Hiroyasu Yoshizawa: "A Low Power 622MHz CMOS Phase-Locked Loop with Source-coupled VCO and Dynamic PFD" IEICE Transaction on Fundamentals. E80-A・6. 1015-1020 (1997)

Hiroyasu Yoshizawa：“具有源耦合 VCO 和动态 PFD 的低功耗 622MHz CMOS 锁相环”IEICE E80-A・6 基础知识 (1997)。

Ikuo Seki: "A Design of First-Order Delay-Line DPLL in 1.2um CMOS Technology" Research Reports on ISEE,Kyushu University. 1. 45-50 (1996)

Ikuo Seki：《A Design of First Order Delay-Line DPLL in 1.2um CMOS Technology》九州大学ISEE研究报告。

工藤 洋介: "構造設計に基づくHEMTの特性計算とモデリングの計算" 九州大学院システム情報科学研究科報告. 3(印刷中). (1998)

工藤洋介：“基于结构设计的HEMT的特性计算和建模计算”九州研究生院系统与信息科学研究生院报告3（出版中）。