New Directions in Sequential Synthesis and Optimization

这项研究探索了一套稳健的逻辑综合工具技术，以支持高性能和低功耗时序同步电路的设计自动化。该方法基于一种新的逻辑时序概念，它将重新时序和跨寄存器边界的逻辑优化结合成一种单一的高效优化技术。还在探索用于指定为有限状态机的电路的顺序综合的状态编码。该模型基于最初用一次热代码表示的状态机的符号表示的受控重编码/重定时。这有助于可靠地估计电路成本，例如延迟、功率和顺序可测试性，作为编码的直接函数。这项拟议的工作是与德克萨斯州奥斯汀的Advanced Micro Devices公司合作进行的。

This research explores a set of techniques for robust logic synthesis tools to support the design automation of high-performance and low-power sequential synchronous circuits. The approach is based on a new concept of logic timing, which combines retiming with logic optimization across register boundaries into a single efficient optimization technique. Also being explored is state encoding for sequential synthesis of circuits specified as finite state machines. The model is based on a controlled reencoding/retiming of the symbolic representation of the state machine represented initially with one-hot code. This facilitates a reliable estimation of circuit cost, such as delay, power, and sequential testability, as a direct function of the encoding. The proposed work is being carried out in collaboration with Advanced Micro Devices, Inc. of Austin, TX.