Nanoscale Si Based Crossbar Architecture for Memory and Logic Operations

提出了一种利用金属纳米线交叉杆阵列实现可重构计算的方案，其中每个交叉点的有源组件基于非晶硅(a-Si)-晶态硅(c-Si)异质结构。随着器件集成度达到预期的兆兆比特规模(1012个器件/cm2)，将需要在器件结构和体系结构上进行新的、根本的改变，以满足与纳米级器件相关的缺陷容限和大规模互连的不断升级的需求。可重构的结构，特别是其中的有源元件是在两个纳米线阵列相互交叉的点上形成的滞后电阻的交叉杆结构，已经成为领先的候选结构。交叉开关方案提供了固有的容错能力，因为电路可以很容易地绕过缺陷组件进行重新布线。简单的双端有源器件结构使其适合积极扩展，有可能将逻辑和存储功能集成在同一实体中。在典型的交叉杆结构中，金属纳米线阵列既用作互连又用作接触引线，自组装分子被认为是有源的滞后元件。然而，基于分子的开关存在成品率低、开关速度慢、开关通断比低等严重问题，严重影响了其应用潜力。在该方案中，我们提出了一种基于固态的替代系统，该系统利用a-Si/c-Si异质结作为金属纳米线交叉棒阵列的有源元件。与基于分子的器件相比，硅异质结器件提供了低至纳米级的可扩展性，同时表现出近乎理想的迟滞开关特性，如高成品率、快速开关速度、明确的阈值和高开关比。此外，通过适当的材料工程，可以在我们的器件结构中实现本征整流行为，这是一种消除串扰的特性，在纵横制方案中是非常必要的。所提出的硅异质结构交叉棒阵列将在允许缺陷的可重构架构中提供高达太比特级别的密度，同时在也与现有硅技术兼容的可靠平台上制造。具体地说，将展示具有集成译码设备的高密度、非易失性存储器，这些译码设备将纳米级组件与微规模电子设备接口。还将探索基于纵横制结构的一般逻辑应用，重点是混合纵横制/CMOS法。这项拟议的工作本质上是高度跨学科的，需要与化学家、材料科学家和计算机科学家密切合作。本提案所述活动的研究部分将与旨在扩大拟议研究影响的教育和其他活动密切相关。这项研究将为研究生提供教育和培训机会，他们将接触到最先进的实验技术，并有机会在适当的会议上展示自己的结果。本科生也将例行公事地参与研究。例如，一年级和二年级的本科生将通过密歇根大学的UROP计划直接参与其中，否则他们不会接触到尖端研究。密歇根大学的SROP计划和NSF的REU计划也将为本科生提供暑期研究机会。此外，在研究过程中开发的知识和技术将被纳入PI正在开发的专题课程：纳米电子学导论，该课程同时提供给工程系和科学系的学生。

We propose to implement a scheme for reconfigurable computing using metallic nanowire crossbar arrays, in which the active component at each cross point is based on an amorphous silicon (a-Si) - crystalline silicon (c-Si) heterostructure.As the device integration level reaches the projected terasbit scale (1012 devices/cm2), novel, radical changes in device structures and architectures will be needed to facilitate the escalating demands of defect tolerance and massive interconnects associated with nanoscale devices. Reconfigurable architectures, in particular, crossbar structures in which the active components are hysteretic resistors formed at the points where two nanowire arrays crossing each other, have emerged as a leading candidate. The crossbar scheme offers inherent defect tolerant capability, as the circuit can be easily rerouted around defect components. The simple two-terminal active device structure makes it suitable for aggressive scaling, with the potential that both logic and memory functions can be integrated in the same entity. In a typical crossbar structure, arrays of metallic nanowires are used as both the interconnects and the contact leads, and self-assembled molecules are proposed as the active, hysteretic component. However, switches based on molecules suffer from serious issues such as low yield, slow switching speed and low on/off ratio, which greatly affect their application potential.In this proposal, we present an alternative, solid-state based system that precisely addresses these issues, by utilizing an a-Si/c-Si heterostructure as the active component in a metallic nanowire crossbar array. Compared to molecule based devices, the Si heterostructure devices offer comparable scalability down to nanometer scale, while exhibiting nearly ideal properties for hysteretic switching, such as high yield, fast switching speed, well-defined thresholds and high on/off ratio. Furthermore, intrinsic rectifying behavior, a property that eliminates crosstalk and is highly desirable in the crossbar scheme, can be achieved in our device structure through proper material engineering. The proposed Si heterostructure crossbar arrays will offer up to terabit-scale density in a defect tolerant, reconfigurable architecture, while being fabricated on a reliable platform that is also compatible with available Si technology. In particular, high density, non-volatile memories with integrated decoder devices that interface the nanoscale components with microscale electronics will be demonstrated. General logic applications based on the crossbar structures will also be explored, with emphasis on a hybrid crossbar/CMOS approach. The proposed work is highly interdisciplinary in nature, and requires close collaboration with chemists, materials scientists, and computer scientists. The research component of the activities described in this proposal will be closely tied to educational and other activities intended to broaden the impact of the proposed research. The research will provide educational and training opportunities for a graduate student who will be exposed to state-of-the-art experimental techniques and given a chance to present his or her results at appropriate conferences. Undergraduates will be routinely involved in the research as well. For example, first and second year undergraduates, who would not otherwise be exposed to cutting-edge research, will be directly involved through U-M's UROP program. Summer research opportunities will also be offered to undergraduates through U-M's SROP program and NSF's REU program. Furthermore, knowledge and techniques developed during research will be incorporated into the special topics course the PI is developing: Introduction to Nanoelectronics, which is offered to students in both engineering and science divisions.