SHF: Small:Energy-Optimized Memory Hierarchies

21世纪初，电力和能源是计算机系统性能和成本不断提高的核心挑战。从手持移动设备到支持它们的数据中心，计算机架构师必须发明新的节能技术，以促进未来科学、教育、政府和商业领域的创新。在当前的系统中，存储和移动计算使用和产生的数据值的内存层次结构比计算本身消耗更多的能量。例如，根据值存储在内存层次结构中的位置，获取双精度乘加运算的操作数可能会消耗1.7到200倍的操作能量。提高存储器层次结构的能源效率不仅可以推动未来计算机系统的发展，还可以减少温室气体的排放。该项目寻求新颖的内存层次设计，以最大限度地减少功率和能量，而不是传统的专注于减少延迟和/或带宽。这些设计基于三个关键假设：(1)缓存存储器可以比延迟或带宽减少更多的能量，(2)优化延迟在可以容忍的情况下变得不那么重要，以及(3)重叠活动不节省电力，但可以节省能源，因为静态功耗。最初的研究方向包括：(1)使用混合虚拟/物理缓存减少地址转换能量的技术，该技术消除了在每次内存访问时访问高度关联的TLB的需要；(2)使用数据压缩技术的节能缓存层次结构，以较低的压缩和解压缩开销取代丢失的高能量成本。这项研究还将扩展广泛使用的开源gem5模拟基础设施，以更准确地模拟新兴内存层次结构的功率和能量。

The early 21st century finds power and energy as the central challenges to continued improvements in computer system performance and cost. From handheld mobile devices to the data centers that support them, computer architects must invent new energy-efficient techniques to facilitate future innovations in science, education, government and commerce. In current systems, the memory hierarchy-which stores and moves the data values used and produced by the computation-consumes more energy than the computation itself. For example, obtaining operands for a double-precision multiply-add can consume 1.7 to 200 times the operation's energy depending on where in the memory hierarchy the values are stored. Improving the energy-efficiency of memory hierarchies can not only enable advances in future computer systems, but also reduces the emission of greenhouse gases.This project seeks novel memory hierarchy designs that minimize power and energy, rather than the classical focus on reducing latency and/or bandwidth. These designs build on three key hypotheses: (1) cache memories can reduce energy more than either latency or bandwidth, (2) optimizing latency becomes less important when it can be tolerated, and (3) overlapping activity does not save power, but can save energy due to static power dissipation. Initial research directions include (1) a technique to reduce address translation energy using a hybrid virtual/physical cache that eliminates the need to access a highly-associative TLB on every memory access and (2) energy-efficient cache hierarchies that use data compression techniques to replace the high energy cost of misses with lower compression and decompression overheads. This research will also extend the widely-used open-source gem5 simulation infrastructure to more accurately model the power and energy of emerging memory hierarchies.