Radio frequency multilevel switching mode power amplifiers with pulse-position and pulse-width modulation for efficient power amplification of broadband mobile communication signals

高效线性射频功率放大器是无线和移动的互联世界的关键组件。效率和线性度对于经典的A类、B类和C类功率放大器的设计是对立的性质。提高效率的当前方法是包络跟踪，即，电源电压跟踪RF输出信号的包络。包络跟踪需要一个快速高效的电源电压调制器。对于带宽超过100 MHz的移动的通信信号，这种调制器的设计越来越具有挑战性。由二进制信号驱动的RF开关模式功率放大器（SMPA）提供了同时实现高线性度和效率的机会。发射信号的幅度和相位信息通过脉冲宽度和脉冲位置（PWP）调制器编码为二进制信号的PWP。这种PWPM信号可以驱动开关模式功率放大器。但是基于PWPM和SMPA的放大器系统通常受到有限幅度动态范围的影响，因为由于SMPA输出电压的有限上升和下降时间，非常短的脉冲不能被放大。本项目的数字功率放大器系统的主要思想是将相位和幅度的精细分辨率编码为二进制信号的脉冲宽度和脉冲位置。该脉冲和脉冲位置调制信号被馈送到有效的开关模式功率放大器。幅度的过程分辨率将被编码成多级开关模式PA的几个离散输出电压电平（VM-SMPA）或输出电流电平（CM-SMPA）。与包络跟踪系统相比，不需要快速电源电压调制器，本课题的主要目标是研究电压模式和电流模式下的高频多电平开关功率放大器，并采用脉宽和脉位调制信号驱动它们，为了实现高动态范围、高效率、高线性度的高频信号放大，需要分三步实现。首先，在28 nm-FDSOI-CMOS工艺中，评估和设计了具有多个输出信号电平的电压和电流模式的新型高频开关模式功率放大器电路拓扑。然后，一个现有的脉冲宽度和脉冲位置调制器集成电路将被用作驱动器的设计多级开关模式功率放大器。最后，将通过由作为基带信号源的FPGA、现有的PWPM-IC和实现的高频多级开关模式功率放大器组成的放大器系统来演示具有高带宽和高带宽效率的移动的通信和无线信号。该项目中涉及的频率范围在450 MHz和6 GHz之间，目标输出信号带宽高达400 MHz。

Efficient and linear radio-frequency power amplifiers are a key component for the wireless and mobile connected world. Efficiency and linearity are antagonistic properties for the design of classical class A, B and C power amplifiers. A current method to increase the efficiency is envelope tracking, i.e. the supply voltage tracks the envelope of the RF output signal. Envelope tracking needs a fast and efficient supply voltage modulator. The design of such modulator is increasingly challenging for the mobile communication signals with bandwidths over 100 MHz. RF switching mode power amplifiers (SMPA), driven by binary signals, offer the opportunity to achieve high linearity and efficiency simultaneously. The amplitude- and phase information of the transmit signal is encoded into the pulse width and pulse position (PWP) of a binary signal by means of a PWP-modulator. Such PWPM signals can drive switching mode power amplifiers. But amplifier systems based on the PWPM and SMPA usually suffer from a limited amplitude dynamic range, as very short pulses can’t be amplified due to the limited rise and fall times of the SMPA output voltage. The main idea behind in the digital power amplifier system of this project is to encode the phase and the fine resolution of the amplitude into the pulse width and pulse position of a binary signal. This pulse-with and pulse-position modulated signal is fed to an efficient switching mode power amplifier. The course resolution of the amplitude will be encoded into few discrete output voltage- (VM-SMPA) or output current levels (CM-SMPA) of a multilevel switching mode PA. Compared to the envelope tracking system a fast supply voltage modulator is not necessary.The main goal of this project is to do research on high frequency multilevel-switching mode power amplifiers (ML-SMPA) in voltage mode and in current mode and to drive them with pulse width and pulse position modulated signals, in order to amplify high frequency signals with high dynamic range with high efficiency and high linearity.Three steps shall reach this goal. At first, new high frequency switching mode power amplifier circuit topologies in voltage- and current mode with several output signal levels are evaluated and designed in a 28 nm-FDSOI-CMOS technology. Then an existing pulse width- and pulse position modulator-IC will be used as driver for the designed multilevel-switching mode power amplifiers. Finally, mobile communication- and wireless signals with high bandwidth and high bandwidth efficiency shall be demonstrated by a amplifier system consisting of a FPGA as base band signal source, the existing PWPM-IC and the realized high frequency multilevel switching mode power amplifiers. The frequency range addressed in this project is between 450 MHz and 6 GHz and the targeted output signal bandwidth is up to 400 MHz.