A Study on Beyond-Binary Computing

目前的超大规模集成电路系统是基于二进制（基数-2）算法与二进制逻辑器件相结合而设计的。随着VLSI技术缩小到深亚微米几何结构，由布线复杂性和延迟增加引起的性能瓶颈变得非常严重。本研究项目旨在通过采用一种名为“超越二进制计算”的新计算范式来研究克服性能瓶颈的可能性。以下是本项目的主要成果：提出了基于非二进制冗余数系统的高速算法，并通过实验芯片的制作验证了算法的性能。示例包括(i)基数4并行分频芯片，（ii）基数2-4-8 CORDIC处理器芯片，（iii）使用SW算法的可配置数据路径芯片，以及（iv）使用冗余复杂算法的实/复可重构数据路径芯片。优化目标应用程序的数字表示，可以大大减少计算时间、功耗和布线复杂性。通过现场可编程数字滤波集成电路的设计，论证了多值逻辑集成电路技术与冗余算法相结合的影响。提出了设计超二进位电路和系统的CAD新技术。设计并制作了以伪随机序列为信息载体的集值逻辑系统原型。制造系统的基本原理被扩展到片内CDMA通信技术，这将有助于实现高度并行计算架构，降低布线复杂性。开发了酶晶体管电路的计算机模拟和分析技术。这些技术被用来演示分子计算的一些应用，包括最优路径规划和图像处理。实验证实了利用酶晶体管等人工催化剂器件实现无线电路集成的原理。少

The present-day VLSI systems are designed on the basis of binary (radix-2) arithmetic algorithms combined with binary logic devices. As the VLSI technology scales down to deep sub-micron geometry, performance bottlenecks caused by increased wiring complexity and delay are becoming significantly severe. This research project is to investigate a possibility of overcoming the performance bottlenecks by employing a new computing paradigm called "Beyond-Binary Computing". Listed below are major results of this project:1. High-speed arithmetic algorithms using non-binary redundant number systems were developed and their performances were confirmed through experimental chip fabrications. Examples include (i) a radix-4 parallel divider chip, (ii) a radix-2-4-8 CORDIC processor chip, (iii) a configurable datapath chip using SW arithmetic, and (iv) a real/complex reconfigurable datapath chip using redundant complex arithmetic. Optimizing number representation for target applications makes possib … More le drastic reduction in computation time, power consumption and wiring complexity. Impacts of multiple-valued logic IC technology combined with redundant arithmetic algorithms were demonstrated through the design of field-programmable digital filter ICs. Also, new CAD techniques for designing beyond-binary circuits and systems were proposed.2. A prototype of set-valued logic system, which uses pseudo-random sequences as information carriers, was designed and fabricated. The underlying principle of the fabricated system was extended to intra-chip CDMA communication techniques, which will be useful for implementing highly parallel computing architectures with reduced wiring complexity.3. Techniques for computer-based simulation and analysis for enzyme transistor circuits were developed. These techniques were used to demonstrate some applications of molecular computing, including optimal path planning and image processing. The principle of wire-free circuit integration using artificial catalyst devices, such as enzyme transistors, was confirmed experimentally. Less