Study on Next Generation FPGA toward Reconfigurable Computing
Study on Next Generation FPGA toward Reconfigurable Computing
批准号:
11490028
负责人:
SUEYOSHI Toshinori
金额:
$9.41万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
1999
资助国家:
日本
项目状态:
已结题
起止时间:
1999 至 2001
中文摘要
正如研究计划中所提到的,我们研究了面向可重构计算的下一代FPGA。以下是本研究的主要结果。下一代FPGA的设计和评估的要求,下一代FPGA的可重构计算进行了检查,使用商业FPGA。设计了下一代FPGA的基本结构,并对其进行了定量评估。详细地,面积利用率,延迟时间和实现密度进行了评估使用实际电路,然后提出了一种新的逻辑块适合下一代FPGA。FPGA提供了多上下文、多粒度/集群的功能,并提出了配置数据缓存的方法。与传统逻辑块相比,提高了实现密度和实现效率,减少了配置数据的使用.建设发展环境,支持我们的发展 ...更多信息 基于软硬件协同设计方法,构建了面向可重构计算的下一代FPGA开发环境--Rosted Next Generation FPGA AA。开发了多上下文提取工具和技术映射工具,有效地利用了本研究开发的下一代FPGA逻辑块的各种功能.可重构计算的可行性研究开发了多媒体使用的实际应用程序,并通过产学合作进行了可行性实验。此外,软件无线电在通信设备领域的可行性进行了检查,并使用商业FPGA进行了调查。从这些结果中,下一代FPGA的可重构计算的潜在可能性是肯定的。利用IEEE1149.1的ISP功能和JAVA的优点,开发了远程控制设备重构技术,并通过可行性实验验证了其有效性。少
英文摘要
As mentioned in the research plan, we studied on next generation FPGA toward reconfigurable computing. The following are major results of the research.1. Design and evaluation of a next generation FPGARequirements for a next generation FPGA toward reconfigurable computing were examined using commercial FPGAs. Moreover, basic architecture for a next generation FPGA were designed, and their quantitative evaluations were performed. In detail, area utilization, delay time, and implementation density were evaluated using practical circuits, and then a novel logic block suitable for next generation FPGA was proposed. The FPGA provides functions of multi-context, multi-grain/cluster, and configuration data cache was proposed. Furthermore, the following were made clear : the implementation density and the implementation efficiency were improved as compared with conventional logic block, and utilization of configuration data was reduced.2. Building a development environment and supporting our p … More roposed next generation FPGAA development environment of next generation FPGA for reconfigurable computing was built based on hardware/software co-design method. The multi-context extract tool and the technology-mapping tool were developed that effectively utilized various functions of the logic block for next generation FPGA we developed in this study.3. Feasibility study on reconfigurable computingThe practical applications for multimedia use were developed, and the feasibility experiment was executed by industry-university co-operation. Moreover, the feasibility of software radio in the field of communication equipment was examined and the investigation using commercial FPGA was performed. From these results, the potential possibility of next generation FPGA for reconfigurable computing was confirmed. Besides, the device reconfiguration technology by remote control that utilized the merits of ISP function of IEEE1149.1 and the JAVA was developed, and its effectiveness was confirmed through the feasibility experiment. Less
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飯田全広, 末吉敏則: "リコンフィギャラブルロジックにおけるLUTの最適粒度に関する一検討"電子情報通信学会技術研究報告. VLD2000-82. 77-82 (2000)
Masahiro Iida、Toshinori Sueyoshi:“可重构逻辑中 LUT 的最佳粒度的研究”IEICE 技术报告 77-82 (2000)。
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Toshinori Sueyoshi and Masahiro lida: "Configurable and Reconfigurable Computing for Digital Signal Processing"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol. E85-A, No. 3. 591-599 (2002)
Toshinori Sueyoshi 和 Masahiro lita:“数字信号处理的可配置和可重新配置计算”IEICE 电子、通信和计算机科学基础汇刊。
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末吉敏則,飯田全広: "リコンフィギャラブル・コンピューティング"情報処理学会誌. 40巻8号. 777-782 (1999)
Toshinori Sueyoshi、Masahiro Iida:“可重构计算”日本信息处理学会杂志,第 40 卷,第 8 期。777-782 (1999)
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末吉敏則: "プログラマブルロジックデバイス-過去から未来へ-"電子情報通信学会 信学技法. CAS2001-96. 17-24 (2002)
Toshinori Sueyoshi:“可编程逻辑器件 - 从过去到未来”电子、信息和通信工程师研究所,IEICE 技术。17-24 (2002)。
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Masahiro IIDA, Toshinori Sueyoshi: "A Novel Programmable Logic Architecture for Reconfigurable Computing"Proc. of Pan-Yellow-Sea International Workshop on Information Technologies for Network Era (PYIWIT'02). 283-290 (2002)
Masahiro IIDA、Toshinori Sueyoshi:“用于可重构计算的新型可编程逻辑架构”Proc。
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共 23 条
Development of Self-Repair Dependable system on FPGA
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批准号:22300018
-
项目类别:Grant-in-Aid for Scientific Research (B)
-
资助金额:$11.81万
-
财政年份:2010
-
负责人:SUEYOSHI Toshinori
-
依托单位:
Research for Reconfigurable System Technology using Fine Grained Cell Architecture
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批准号:17300021
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$10.08万
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财政年份:2005
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负责人:SUEYOSHI Toshinori
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依托单位:
Research and Development of Flexible Hardware and Remote Reconfiguration Techniques
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批准号:14390041
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$7.04万
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财政年份:2002
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负责人:SUEYOSHI Toshinori
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依托单位:
Study of Reconfigurable Processor using Programmable LSI
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批准号:09680344
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.05万
-
财政年份:1997
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负责人:SUEYOSHI Toshinori
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依托单位:
Rapid Prototyping Technology for Large Scale Logic Circuits
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批准号:09559014
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$8.32万
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财政年份:1997
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负责人:SUEYOSHI Toshinori
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依托单位:
Study of Cluster Computing on a High Speed Network Environment
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批准号:07680365
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$1.47万
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财政年份:1995
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负责人:SUEYOSHI Toshinori
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依托单位:
Study on Interconnection Networks Towards Realization of a Reconfigurable Parallel Computer
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批准号:05680278
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项目类别:Grant-in-Aid for General Scientific Research (C)
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资助金额:$1.28万
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财政年份:1993
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负责人:SUEYOSHI Toshinori
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依托单位:
Study on the Speed-Up of Communications Protocol Processing by Parallel Processing
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批准号:01460256
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项目类别:Grant-in-Aid for General Scientific Research (B)
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资助金额:$3.33万
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财政年份:1989
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负责人:SUEYOSHI Toshinori
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依托单位:
海外基金