Design of Electronic Properties and Development of High-Mobility Channel Technology for Low Power/High-Speed Nano-CMOS Devices

为了实现低功耗和高速CMOS器件，我们研究了应变Ge和GeSn外延层的晶体生长和电子特性。我们通过衬底设计、低温生长和应变工程实现了极高Sn含量的GeSn生长和GeSn外延层中缺陷密度的降低。我们还开发了GeSn材料的点缺陷、载流子特性和MOS界面的工程技术。此外，我们展示了GOI和SGOI晶片的制造和这些层中载流子迁移率的改善。

We have investigated the crystal growth and electronic properties of strained Ge and GeSn epitaxial layers for realizing low power and high speed CMOS devices. We achieved the growth of very high Sn content GeSn growth and the reduction of defect density in GeSn epitaxial layers by substrate design, low temperature growth, and strain engineering. We also developed engineering technology of point defects, carrier properties, and MOS interface for GeSn materials. In addition, we demonstrated the fabrication of GOI and SGOI wafers and the improvement on the carrier mobility in those layers.