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A Study of Metal/Insulator/Semiconductor Super-Heterostructure Material Systems for Multifunctional Electron Devices

多功能电子器件金属/绝缘体/半导体超异质结构材料体系研究

基本信息

批准号：
13555089
负责人：
ASADA Masahiro
金额：
$ 8.19万
依托单位：
Tokyo Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2002
项目状态：
已结题

项目摘要

This project aimed at fabrication of electron devices using metal/insulator/semiconductor heterostructures, in which the quantum effect takes place remarkably, and achievement of their high functional operations, in order to promote the down sizing and high density of large scale integrated circuits. The results are summarized as follows.Crystal growth of resonant tunneling structures for the quantum-effect devices was investigated by choosing CaF2/CdF2/Si heterostructure system in which high on-off ratio and multi-functional operation are expected due to large potential barrier and sharp quantized energy levels. In order to precisely control the thickness of the epitaxial layer in the nano-scale range, we proposed nano-area local epitaxy in which the growth area is restricted in 100nm-order region of the surface. By this technique, remarkable uniformity of the characteristics was achieved, and systematic experiments for the structure dependence of the electrical characteristics became … More possible for the first time. By using hydrogen-terminated substrate, the resonant tunneling structure was grown on Si(100) substrates. The negative differential resistance was obtained for the first time at room temperature for this material system on Si(100). The negative differential resistance on Si(100) was also obtained with high reproducibility using inclined substrates with an appropriate off angle by which the anti-phase boundary is less included in the grown layers.Vertical MOSFETs integrated with CaF2/CdF2/Si low-current density resonant tunneling diode between the gate and source electrodes were proposed. 50% reduction of the device area was shown to be possible in the SRAM by this structure compared with the circuits with MOSFETs only. The vertical MOSFETs with PtSi Schottky source/drain was fabricated using beam lithography. The room temperature operation was achieved for the devices with 55nm-long gates, 5 and 8nm-thick gate oxides, and 8-30nm-long channels. CaF2/CdF2 triple-barrier resonant tunneling diodes were integrated these vertical transistors, and electrical characteristics attributed to the resonant tunneling was obtained at room temperature. Less

本计画旨在利用金属/绝缘体/半导体异质结构制造出量子效应显著的电子元件，并实现其高功能操作，以促进大规模积体电路的小型化与高密度化。主要研究结果如下：选择CaF_2/CdF_2/Si异质结体系，研究了量子效应器件中共振隧穿结构的晶体生长。为了在纳米尺度范围内精确控制外延层的厚度，我们提出了纳米区域局域外延，其中生长区域被限制在表面的100 nm量级区域内。通过这种技术，实现了特性的显著均匀性，并且对电特性的结构依赖性进行了系统的实验， ...更多信息第一次有可能。采用氢封端衬底，在Si（100）衬底上生长了共振隧穿结构。该材料体系在室温下首次在Si（100）衬底上获得了负微分电阻。在Si（100）衬底上采用倾斜衬底，通过适当的偏角，生长层中包含的反相边界较少，获得了高重复性的负微分电阻。提出了在栅源电极之间集成CaF2/CdF2/Si低电流密度共振隧穿二极管的垂直MOSFET。结果表明，与仅采用MOSFET的电路相比，采用这种结构的SRAM器件面积可减少50%。采用束流光刻技术制作了PtSi肖特基源/漏垂直MOSFET。栅长为55nm，栅氧化层厚度为5和8nm，沟道长度为8 - 30nm的器件实现了室温工作。将CaF2/CdF2三势垒共振隧穿二极管集成到这些垂直晶体管中，并在室温下获得了归因于共振隧穿的电学特性。少