Low-Power and High-Performance Processor based on Co-optimization of Architecture and Compiler

本研究的目的是通过对内存层次结构的使用进行编译器优化来实现高性能和低功耗。首先，我们提出了一种新的存储器结构，在处理器芯片上实现了软件控制存储器和缓存存储器。通过使用软件控制的内存，编译器可以优化内存层次之间的数据传输，减少芯片外内存流量的功耗。为了在不降低性能的前提下降低功耗，提出了一种新的寄存器文件机制。其次，我们提出了一种细粒度关闭上述新存储器电压供应的机制。第三，我们开发了一种新的编译算法，该算法与上述架构协同工作，以获得更高的性能和更低的功耗。处理器的能量消耗包括动态能量和静态能量。由于这两项独立依赖于软件控制内存的使用率，因此不能通过最小化它们中的任何一个来获得最小能量。此外，静态能量很大程度上取决于温度。因此，我们提出了一种新的温度感知编译技术。该技术预先计算了内存使用率与工作温度之间的关系。然后，对给定的源代码进行优化，通过监测运行温度并使用预先计算的关系动态选择最佳内存使用率。我们开发了一个环境来评估我们的架构和编译算法的有效性。评估结果表明，我们的协同优化策略可以成功地降低功耗并实现高性能。

The purpose of this research is to achieve high performance and low power consumption by using compiler optimization on the usage of memory hierarchy. First, we proposed a new memory architecture which implements both software controlled memory and cache memory on a processor chip. By using the software controlled memory, compiler can optimize the data transfer between memory hierarchies and reduce power-wasting off-chip memory traffic. A new mechanism of register file is also proposed to reduce power consumption with little performance degradation. Second, we proposed a mechanism to shut down the voltage supply of the above new memory with fine granularity. Third, we developed a new compilation algorithm which co-operates with the above architecture for higher performance and lower power consumption. Energy consumption of a processor consists of dynamic energy and static energy. Because these two terms depend on the usage ration of software controlled memory independently, the least energy cannot be derived by minimizing either of them. Furthermore, static energy heavily depends on temperature. Thus, we propose a a new temperature aware compilation technique. The technique pre-computes the relationship between the memory usage ratio and operating temperature. Then, given source codes are optimized to select the best memory usage ratio dynamically by monitoring the operating temperature and by using the pre-computed relationship. We developed an environment to evaluate the effectiveness of our architecture and compilation algorithm. The evaluation results revealed that our co-optimization strategy can successfully reduce power consumption and achieve high performance.