酸化濃縮法を用いた高性能薄膜Ｇｅ－Ｏｎ－Ｉｎｓｕｌａｔｏｒ　ＦＥＴに関する研究

我们提出并演示了一种新的通道应变控制技术，该技术能够在同一衬底上实现高性能的拉伸应变Ge-on-insulator (GOI) n- mosfet和压缩应变GOI - p- mosfet。结果表明，Ge缩合后850℃的额外氧化使GOI中的应变条件由1.8%的压缩应变变为0.5%的拉伸应变，电子迁移率提高了2.1。此外，减薄GOI通道厚度引入了由于GOI波段调制而导致的显著迁移率增强，导致在GOI厚度为2.5 nm的n- mosfet中电子迁移率达到777 cm2/Vs。为了提高p- mosfet的性能，研究了Ge凝聚形成（110）取向SGOI的方法。结果表明，无论从应变角度还是从Ge分数角度来看，Ge分数为54%的SGOI都能使孔洞迁移率达到最大。与目前报道的平面GOI/SGOI p- mosfet相比，压缩应变（110）27 nm厚Si0.46G0.54OI p- mosfet的空穴迁移率达到了837 cm2/Vs。此外，对于5 nm厚的极薄体（110）Si0.46G0.54OI p- mosfet，仍然保持295 cm2/Vs的高空穴迁移率。因此，我们的上述研究内容在2019年国际电子器件会议（IEDM）上进行了报告，这是研究领域最著名的会议之一。

We propose and demonstrate a new channel strain control technology enabling to realize both high performance tensile strain Ge-on-insulator (GOI) n-MOSFETs and compressive strain GOI p-MOSFETs on a same substrate. It is found that additional oxidation at 850 oC after Ge condensation changes the strain condition in GOI from 1.8 % compressive strain to 0.5% tensile strain, resulting in the electron mobility enhancement of 2.1. Furthermore, thinning GOI channel thickness introduces significant mobility enhancement attributable to GOI band modulation, leading to electron mobility of 777 cm2/Vs in n-MOSFETs with GOI thickness of 2.5 nm. For performance enhancement of p-MOSFETs, (110)-oriented SGOI formation by Ge condensation is studied. It is found that SGOI with the Ge fraction of 54 % maximizes the hole mobility from the viewpoints of both strain and Ge fractions. Record high hole mobility of 837 cm2/Vs is demonstrated with compressive strain (110) 27-nm-thick Si0.46G0.54OI p-MOSFETs, compared with mobility in planar GOI/SGOI p-MOSFETs reported so far. In addition, high hole mobility of 295 cm2/Vs is still maintained for 5-nm-thick extremely-thin body (110) Si0.46G0.54OI p-MOSFETs.As a result aforementioned contents of our research were reported at 2019 International Electron Devices Meeting (IEDM), which is one of most famous conferences in the research field.