SHF: Small: Efficient and Accurate Methodologies for Unifying the Layout, Device Simulation, and Process Simulation Worlds

由于MOSFET的短沟道行为严重退化，英特尔和台积电已宣布在即将到来的技术节点转向多栅极FET。多门器件和较大电路的硬件实验需要非常高的成本和周转时间。因此，迫切需要针对此类器件/电路的基于高效预测性3D技术CAD（3D-TCAD）的工艺/器件表征方法。目前缺乏这种方法严重阻碍了这一领域的迅速进展。虽然基于3D-TCAD的探索对于准确的预测建模是必不可少的，但它受到重大挑战的困扰，这使得有必要开发一套与3D-TCAD生态系统集成的无缝方法/算法，以快速解决工艺，布局和器件级问题。拟议工作的主要目的是开发有效和准确的方法，统一布局，2D/3D器件模拟和工艺模拟世界，从而首次扩大了多栅极器件预测建模的范围，超越了多器件TCAD障碍，这是较低技术节点的主要亮点。该项目旨在开发一套通用的方法，用于合成与给定布局对应的连续2D/3D器件模拟就绪结构，而无需对每个布局进行重复和昂贵的3D工艺模拟。这些方法预计将产生几个数量级的加速TCAD结构生成的大型布局，与运行时间从天/周减少到几个小时，每个设计和减少内存占用。该项目还将开发快速缓存-外推-更新技术，以缓解混合模式和连续3D器件模拟的迭代线性求解器的收敛问题。本研究开发的方法将打破多器件TCAD的障碍，并通过将布局与工艺/器件模拟统一起来，使准确和高效的预测3D-TCAD成为可能。所制定的方法/工具将通过网络、会议和期刊传播。该材料将被纳入PI在普林斯顿大学教授的纳米技术设计课程。普林斯顿大学有本科生独立研究的传统。许多高年级的学生都希望做他们的研究项目在这个主题。女性和少数民族学生将通过普林斯顿大学的奖学金计划被吸引到这项研究中来。还计划为高中学生开展进一步的外联活动。

Due to the severely degraded short-channel behavior of MOSFETs, Intel and TSMC have announced their switch to multi-gate FETs at the upcoming technology nodes. Hardware experiments with multi-gate devices and larger circuits entail very high cost and turnaround time. Thus, efficient predictive 3D-Technology CAD (3D-TCAD) based process/device characterization methods for such devices/circuits are urgently needed. A lack of such methods currently poses a significant impediment to rapid progress in this area. Though 3D-TCAD based exploration is essential for accurate predictive modeling, it is beset with major challenges which makes it necessary to develop a seamless set of methodologies/algorithms integrated with 3D-TCAD eco-systems for resolving process, layout, and device level issues quickly. The main aim of the proposed work is to develop efficient and accurate methodologies for unifying the layout, 2D/3D device simulation, and process simulation worlds, thereby, for the first time, expanding the horizon of predictive modeling for multi-gate devices beyond the many-device TCAD barrier, which is a major showstopper at lower technology nodes. The project aims to develop a set of versatile methodologies for synthesizing contiguous 2D/3D device-simulation-ready structures corresponding to given layouts, without the need for repetitive and expensive 3D process simulations on each layout. These methodologies are expected to yield several orders of magnitude speedup in TCAD structure generation for large layouts, with run-time reduction from days/weeks to a few hours per design and decreased memory footprints. The project will also develop fast cache-extrapolate-update techniques to alleviate the problem of obtaining convergence with iterative linear solvers for both mixed-mode and contiguous 3D device simulation.The methodologies developed in this research will break the many-device TCAD barrier and, by unifying layout with process/device simulation, make accurate and efficient predictive 3D-TCAD possible. The methodologies/tools that are developed will be disseminated through the web, conferences and journals. The material will be included in a course on Design with Nanotechnologies that the PI teaches at Princeton University. Princeton has a tradition of undergraduate independent research. Many senior students are expected to do their research project on this topic. Female and minority students will be attracted to this research through Princeton's Fellowship Program. Further outreach activities are also planned for high-school students.