A STUDY OF ULTRASMALL DEVICE CONTAINING NANOMETER-CONTROLLED Si-Ge HETEROLAYER

本研究的目的是构建一种含有纳米控制的Si_<1-x>Ge_x异质层的高性能超小型器件的制备工艺。研究结果总结如下:(1)利用超净热壁低压CVD系统，在最干净的SiH_4、GeH_4和H_2或Ar反应环境下，实现了Si/Si_<1-x bb_0 Ge_x/Si异质结构的极低温外晶生长过程，该异质结构具有原子平面和Ge组分在Si（100）上的界面。相对较低的沉积温度适合于较高的Ge组分，以防止沉积过程中层的岛状生长。在550、500和450的温度下，分别获得了Si_<0.8>Ge_<0.2>、Si_<0.5>Ge_<0.5>和Si_<0.3>Ge_<0.7>的原子平面和界面。(2)在10nm厚Si/7nm厚Si_<1-x>Ge_x/Si异质结构上，采用自配Si栅极工艺，在700℃以下的温度下制备了MOSFET。与没有sige沟道的MOSFET相比，实现了Si_<0.5>Ge_<0.5>沟道的高性能MOSFET，在300K时迁移率提高了约70%，在77K时迁移率提高了150%以上。(3)在3x10^<17>-2x10^<20>cm^<-3>范围内实现了Si_<1-x>Ge_x层的原位B掺杂控制。结果表明，Si_<0.75>Ge_<0.25>薄膜的霍尔迁移率最小，且Si_<0.75>Ge_<0.25>薄膜的迁移率与未应变薄膜的迁移率基本相等。(4)在550℃的温度下实现了In-sity B掺杂SiGe的选择性外延生长。利用这种选择性薄膜，形成了具有低水平反向电流密度（10^<-10> a /cm^2）的高性能自对准超浅结。因此，可以改善栅极和源极漏极之间的重叠控制以及对超小型MOSFET短沟道效应的抑制。

The object of this research is to construct the fabrication process of a high performance ultrasmall device containing nanometer controlled Si_<1-x>Ge_x heterolayr. The research results are summarized as follows.(1) A very low-temperature epitaxial growth process of the Si/Si_<1-x>Ge_x/Si heterostructure with atomically flat surfaces and interfaces for Ge fractions on Si(100) has been achieved under the cleanest possible reaction and interfaces for Ge fracions on Si(100) has been achieved under the cleanest possible reaction environment of SiH_4, GeH_4 and H_2 or Ar using an ultraclean hot-wall low-pressure CVD system. A relatively lower deposition temperatures were suitable for higher Ge fractions in order to prevent island growth of thelayrs during deposition. Atomically flat surfaces and interfaces for the heterostructure containing Si_<0.8>Ge_<0.2>, Si_<0.5>Ge_<0.5> and Si_<0.3>Ge_<0.7> layrs were obtained by deposition at 550, 500 and 450ﾟC, respectively.(2) MOSFET's were fabricated at temparetures below 700ﾟC on the 10nm-thick Si/7nm-thick Si_<1-x>Ge_x/Si heterostructure using a self-alligned Si gate process. A high performance Si_<0.5>Ge_<0.5>-channel MOSFET has been achieved with a large mobility enhancement of about 70% at 300K and over 150% at 77K compared with that of a MOSFET without SiGe-channel.(3) In-situ B doping control of Si_<1-x>Ge_x layr was achieved in the range of 3x10^<17>-2x10^<20>cm^<-3>. It was found that Hall mobility has a minimum value for Si_<0.75>Ge_<0.25> film, and the mobility of the strained Si_<0.75>Ge_<0.25> film is neary equal to that of the unstrained one.(4) In-sity B doped selective SiGe epitaxial growth were achieved at 550ﾟC.Using this selective film, high performance self-aligned ultrashallow junction was formed with a low level reverse current density, the range of 10^<-10>A/cm^2. As a result, the overlap control between gate and source/drain and suppression of short channel effects in ultrasmall MOSFET can be improved.