A Study of Metal/Insulator/Semiconductor Super-Heterostructure Material Systems for Multifunctional Electron Devices

本项目旨在利用金属/绝缘体/半导体异质结构制造量子效应显著的电子器件，并实现其高功能操作，以促进大规模集成电路的小型化和高密度化。结果总结如下：采用高势垒和高量子化能级的CaF2/CdF2/Si异质结构体系，研究了量子效应器件共振隧道结构的晶体生长。为了在纳米尺度范围内精确控制外延层的厚度，我们提出了将生长区域限制在表面100nm级区域的纳米区域局部外延。通过这种技术，获得了显著的特性均匀性，首次使系统地实验电特性的结构依赖性成为可能。采用端氢衬底，在Si（100）衬底上生长了谐振隧道结构。首次在室温下获得了该材料体系在Si（100）上的负微分电阻。在Si（100）上的负差分电阻也获得了高再现性，使用倾斜衬底具有适当的偏离角，反相边界较少包含在生长层中。提出了在栅极和源极之间集成CaF2/CdF2/Si低电流密度谐振隧道二极管的垂直mosfet。与仅使用mosfet的电路相比，该结构可使SRAM中的器件面积减少50%。采用波束光刻技术制备了具有PtSi肖特基源极/漏极的垂直mosfet。器件的栅极长度为55nm，栅极氧化物厚度为5和8nm，通道长度为8-30nm，实现了室温操作。将这些垂直晶体管集成为CaF2/CdF2三势垒谐振隧道二极管，并在室温下获得了谐振隧道的电学特性。少

This project aimed at fabrication of electron devices using metal/insulator/semiconductor heterostructures, in which the quantum effect takes place remarkably, and achievement of their high functional operations, in order to promote the down sizing and high density of large scale integrated circuits. The results are summarized as follows.Crystal growth of resonant tunneling structures for the quantum-effect devices was investigated by choosing CaF2/CdF2/Si heterostructure system in which high on-off ratio and multi-functional operation are expected due to large potential barrier and sharp quantized energy levels. In order to precisely control the thickness of the epitaxial layer in the nano-scale range, we proposed nano-area local epitaxy in which the growth area is restricted in 100nm-order region of the surface. By this technique, remarkable uniformity of the characteristics was achieved, and systematic experiments for the structure dependence of the electrical characteristics became … More possible for the first time. By using hydrogen-terminated substrate, the resonant tunneling structure was grown on Si(100) substrates. The negative differential resistance was obtained for the first time at room temperature for this material system on Si(100). The negative differential resistance on Si(100) was also obtained with high reproducibility using inclined substrates with an appropriate off angle by which the anti-phase boundary is less included in the grown layers.Vertical MOSFETs integrated with CaF2/CdF2/Si low-current density resonant tunneling diode between the gate and source electrodes were proposed. 50% reduction of the device area was shown to be possible in the SRAM by this structure compared with the circuits with MOSFETs only. The vertical MOSFETs with PtSi Schottky source/drain was fabricated using beam lithography. The room temperature operation was achieved for the devices with 55nm-long gates, 5 and 8nm-thick gate oxides, and 8-30nm-long channels. CaF2/CdF2 triple-barrier resonant tunneling diodes were integrated these vertical transistors, and electrical characteristics attributed to the resonant tunneling was obtained at room temperature. Less