Low-Power and High-Performance Processor based on Co-optimization of Architecture and Compiler

本研究的目的是通过编译器对内存层次的使用进行优化，以达到高性能和低功耗的目的。首先，我们提出了一种新的存储器架构，它实现了软件控制的存储器和高速缓存存储器的处理器芯片上。通过使用软件控制的存储器，编译器可以优化存储器层次之间的数据传输，并减少功耗的片外存储器流量。提出了一种新的寄存器文件机制，在保证性能的前提下降低了功耗。其次，我们提出了一种机制，以关闭上述新的存储器的电压供应与细粒度。第三，我们开发了一种新的编译算法，该算法与上述架构相配合，以提高性能和降低功耗。处理器的能量消耗包括动态能量和静态能量。由于这两项独立地依赖于软件控制存储器的使用率，因此最小能量不能通过最小化它们中的任何一项来获得。此外，静态能量很大程度上取决于温度。因此，我们提出了一种新的温度感知编译技术。该技术预先计算存储器使用率和工作温度之间的关系。然后，给定的源代码进行优化，以选择最佳的内存使用率动态监测的工作温度，并通过使用预先计算的关系。我们开发了一个环境来评估我们的架构和编译算法的有效性。评估结果表明，我们的协同优化策略可以成功地降低功耗，实现高性能。

The purpose of this research is to achieve high performance and low power consumption by using compiler optimization on the usage of memory hierarchy. First, we proposed a new memory architecture which implements both software controlled memory and cache memory on a processor chip. By using the software controlled memory, compiler can optimize the data transfer between memory hierarchies and reduce power-wasting off-chip memory traffic. A new mechanism of register file is also proposed to reduce power consumption with little performance degradation. Second, we proposed a mechanism to shut down the voltage supply of the above new memory with fine granularity. Third, we developed a new compilation algorithm which co-operates with the above architecture for higher performance and lower power consumption. Energy consumption of a processor consists of dynamic energy and static energy. Because these two terms depend on the usage ration of software controlled memory independently, the least energy cannot be derived by minimizing either of them. Furthermore, static energy heavily depends on temperature. Thus, we propose a a new temperature aware compilation technique. The technique pre-computes the relationship between the memory usage ratio and operating temperature. Then, given source codes are optimized to select the best memory usage ratio dynamically by monitoring the operating temperature and by using the pre-computed relationship. We developed an environment to evaluate the effectiveness of our architecture and compilation algorithm. The evaluation results revealed that our co-optimization strategy can successfully reduce power consumption and achieve high performance.