RIA: VLSI Architecture Designs for High-Speed Signal and Image Processing

该项目开发了高速的算法和架构 数字信号和图像处理应用的实现。 基于先前关于前瞻、分解和增量的结果 计算技术的硬件高效实现的高， 快速线性递归和自适应数字滤波器，一种方法是 将这些算法转换为等价形式， 可以在超过原始系统固有限制的采样率下工作 算法 正在对这些技术进行扩展， 非线性递归，例如动态编程，量化器环路， 自适应差分脉冲编码调制和自适应判决 反馈均衡 这些算法的实现位- 串行、半串行和位并行架构目前 正在研究中。 许多实时信号和图像处理中的计算需求 算法只能通过专用的实现来满足。 成功 专用设计需要适当选择算法 架构和实施方法。 一个完整 算法和架构方法的检查，如 这个项目，将提供应用程序特定的设计师广泛的 设计空间，可以利用这些空间来获得更高效的 实现方式的 这项研究将影响未来的集成设计 专用信号和图象的超大规模集成电路实现环境 处理应用程序。

This project develops algorithms and architectures for high-speed implementations of digital signal and image processing applications. Based on previous results on lookahead, decomposition, and incremental computation techniques for hardware-efficient implementation of high- speed linear recursive and adaptive digital filters, a method is developed to transform these algorithms into equivalent forms, which can operate at sample rates beyond the inherent limits in the original algorithms. Extensions are being carried out on these techniques to nonlinear recursions, such as dynamic programming, quantizer loops, adaptive differential pulse code modulation, and adaptive decision feedback equalization. Implementations for these algorithms in bit- serial, nibble-serial, and bit-parallel architectures are currently under study. The computational needs in many real-time signal and image processing algorithms can only be met by dedicated implementations. Success of dedicated designs require appropriate choice of algorithms architectures, and implementation methodologies. A complete examination of the algorithm and architecture approaches, as studied in this project, will provide the application-specific designer a wide design space, which can be exploited to obtain more efficient implementations. This research will impact future integrated design environments for VLSI implementations of dedicated signal and image processing applications.