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FoMR: IPC-MASTA: Boosting IPC with Microarchitectural Support for Tightly-Coupled Accelerators

FoMR: IPC-MASTA: Boosting IPC with Microarchitectural Support for Tightly-Coupled Accelerators
FoMR:IPC-MASTA:通过紧耦合加速器的微架构支持增强 IPC
批准号:
2010830
负责人:
Mikko Lipasti
金额:
$26.99万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2020
资助国家:
美国
项目状态:
已结题
起止时间:
2020-07-01 至 2024-06-30

项目摘要

项目成果

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中文摘要
翻译
50多年来,高性能微处理器的发展为社会带来了无数的好处,包括在许多科学学科和医疗保健服务方面取得了前所未有的进步,提高了经济效率和生产力,创造了新的娱乐形式,并创造了全新的行业和商业模式。然而,计算工业和半导体技术都处于十字路口,需要新的方法来维持性能增长的历史趋势,并克服传统方法在提高处理器性能方面所面临的障碍。在最近的设计中采用的一种很有前途的方法是将特定功能的硬件加速器集成到处理器旁边,从而能够高效和高性能地卸载常见的、粗粒度的、计算密集型的操作,例如来自通用CPU的视频数据解码。本项目将探索这种方法的一种新变体,其中加速器被设计为执行频繁的、细粒度的操作,与处理器核心紧密耦合,并且有望更加灵活、广泛适用,并且更容易集成到当今绝大多数程序员所熟悉的软件开发模型中。随着科学和概念的进步,这项研究预计将导致几个实用的人工制品,这将使未来微处理器的设计者更容易地集成这种加速器,以及准备和培训研究生,他们有可能通过未来的就业直接技术转移。该项目旨在对紧密耦合加速器(tca)进行详细的研究,揭示将它们集成到现代处理器中的权衡和复杂性。迄今为止,对许多可能对整体处理器性能和功耗产生关键影响的设计考虑因素进行表征和优化的工作很少。该项目将分三个阶段解决这个问题。初始阶段将开发一个分析模型,用于评估将tca集成到高性能cpu中的影响。接下来,对tca微架构含义的全面研究将揭示集成tca的关键设计挑战、机遇和新颖解决方案。最后阶段将研究可重构tca,旨在实现专业加速和广泛适用性这两个看似矛盾的目标。该项目将研究使用我们的可重构TCA架构实现通用加速的几种途径,表明它可以在不投入大量硬件资源和设计工作的情况下获得专业化和泛化的最佳效果。该奖项反映了美国国家科学基金会的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Over fifty years of advances in high-performance microprocessors have enabled countless benefits to society, including unprecedented advances in many scientific disciplines and healthcare delivery, improvements in economic efficiency and productivity, new forms of entertainment, and the creation of entirely new industries and business models. However, both the computing industry and semiconductor technology are at a cross-roads, and new approaches are needed to sustain the historical trend of performance increases and overcome the barriers faced by conventional approaches to improving processor performance. A promising approach employed in recent designs has been to integrate function-specific hardware accelerators next to the processor, enabling efficient and high-performance offloading of common, coarse-grained, compute-intensive operations—such as decoding of video data—from the general-purpose CPU. This project will explore an emerging variant of this approach, where the accelerators are designed to perform frequent, fine-grained operations, are coupled tightly to the processor core, and are expected to be more flexible, broadly applicable, and easier to integrate into the software development model familiar to the vast majority of today’s programmers. This research is expected to lead to several practical artifacts along with scientific and conceptual advances that will enable designers of future microprocessors to more easily integrate such accelerators, as well as preparation and training of graduate students with potential for direct technology transfer through their future employment.This project seeks to conduct a detailed study of tightly-coupled accelerators (TCAs), uncovering the trade-offs and complexities of integrating them into modern processors. To date, little has been done to characterize and optimize the many design considerations that can have critical impact on overall processor performance and power consumption. The project will approach this problem in three phases. The initial phase will develop an analytical model for assessing the impact of integrating TCAs in high-performance CPUs. Next, a comprehensive study of the microarchitectural implications of TCAs will uncover key design challenges, opportunities, and novel solutions for integrating TCAs. The final phase will investigate reconfigurable TCAs, which are intended to achieve the seemingly contradictory goals of specialized acceleration as well as broad applicability. The project will investigate several avenues for general-purpose acceleration using our reconfigurable TCA architecture, showing that it is possible to reap the best of both worlds of specialization and generalization without dedicating significant hardware real estate nor design effort.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(10)
专著(0)
科研奖励(0)
会议论文
Modeling Architectural Support for Tightly-Coupled Accelerators
紧耦合加速器的建模架构支持
DOI: 10.1109/ispass48437.2020.00045
发表时间: 2020
期刊: ISPASS Proceedings
影响因子: --
作者: [Schlais, David J., Zhuo, Heng, Lipasti, Mikko H.]
通讯作者: Lipasti, Mikko H.
Value Locality Based Approximation With ODIN
使用 ODIN 进行基于值局部性的近似
DOI: 10.1109/lca.2020.3002542
发表时间: 2020
期刊: IEEE Computer Architecture Letters
影响因子: 2.3
作者: [Singh, Rahul, Ravi, Gokul Subramanian, Lipasti, Mikko, Miguel, Joshua San]
通讯作者: Miguel, Joshua San
Systems-on-Chip with Strong Ordering
具有强排序功能的片上系统
DOI: 10.1145/3428153
发表时间: 2021
期刊: ACM Transactions on Architecture and Code Optimization
影响因子: 1.6
作者: [Puthoor, Sooraj, Lipasti, Mikko H.]
通讯作者: Lipasti, Mikko H.
DOI: 10.1109/dsn-w50199.2020.00016
发表时间: 2019-08
期刊: 2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)
影响因子: --
作者: [Ravi Raju;Mikko H. Lipasti]
通讯作者: Ravi Raju;Mikko H. Lipasti
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