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Research on Software Controlled Integrated Memory Architecture for Large Scientific Computing

Research on Software Controlled Integrated Memory Architecture for Large Scientific Computing
大型科学计算软件控制集成存储架构研究
批准号:
10680335
负责人:
NAKAMURA Hiroshi
金额:
$2.18万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
1998
资助国家:
日本
项目状态:
已结题
起止时间:
1998 至 1999

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项目成果

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中文摘要
翻译
在大规模科学计算中,高性能计算离不开足够的内存吞吐量。在这项研究中,我们提出了一种新的架构,通过将软件可控内存集成到处理器芯片中来提供足够的内存吞吐量。由于集成的片上存储器是由软件显式寻址的,因此只有所需的数据被预先传输到片上存储器中,而不会清除由于常规高速缓存中频繁发生的不幸冲突而导致的其他所需数据。在这一点上,片上存储器比缓存更好地利用了时间局部性。我们为所提出的体系结构开发了一个时钟级模拟器,并通过实际的科学应用对其进行了评估。仿真结果表明,与传统的纯缓存结构相比,该结构能够有效地减少片外存储器的流量,减少了片外存储器的流量。当片外存储器的延迟为40个CPU周期时,该结构的性能提高了2.7倍。片外存储延迟越大,性能改善的程度越大,片外存储延迟增加,片外存储带宽降低。因此,结果表明,提出的体系结构的有效性将在未来继续增长。
英文摘要
Sufficient memory throughput is indispensable for high performance computing in large scale scientific computing. In this research, we propose a new architecture for providing sufficient memory throughput by integrating software controllable memory into processor chip. Since the integrated On-Chip Memory is explicitly addressed by software, only the required data is pre-transferred into the On-Chip Memory without flushing out other required data caused by unfortunate conflicts which occurs frequently in conventional cache. At this point, On-Chip Memory is better to exploit temporal locality than cache.We developed a clock-level simulator for the proposed architecture and evaluated it by using practical scientific applications. In the simulation, various configurations can be explored including the number of functional units, latency and issue rate for each operation, the structure of data cache and On-Chip Memory, and throughput and latency of off-chip memory.The evaluation results by using QCD(Quantum Chromo Dynamics) computation reveals that the proposed architecture decreases off-chip memory traffic compared with conventional cache-only architecture. When the latency of off-chip memory is 40 CPU cycles, the architecture achieves 2.7 times improvement in performance. The degree of the performance improvement increases for longer off-chip memory latency.Off-Chip Memory latency is expected to increase and Off-Chip Memory bandwidth is expected to decrease. Therefore, the results indicate that the effectiveness of the proposed architecture will continue to grow in the future.
期刊论文(21)
专著(0)
科研奖励(0)
会议论文
K. Nakazawa: "CP-PACS : A Massively Parallel Processor at University of Tsukuba"Journal of Parallel Computing. 25. 1635-1661 (1999)
K. Nakazawa:“CP-PACS:筑波大学的大规模并行处理器”并行计算杂志。
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P. Panda: "Augmenting Loop Tiling with Data Alignment for Improved Cache Performance"IEEE Transactions on Computers. Vol. 48 No. 2. 142-149 (1999)
P. Panda:“通过数据对齐增强循环平铺以提高缓存性能”IEEE Transactions on Computers。
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通讯作者:
P. Panda: "Augmenting Loop Tiling with Data Alignment for Improved Cache Performance"IEEE Transactions on Computers. Vol.48, No.2. 142-149 (1999)
P. Panda:“通过数据对齐增强循环平铺以提高缓存性能”IEEE Transactions on Computers。
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