CAREER: Gate-Level Performance Optimization of Pipelines and General Sequential Circuits

本课题研究的是高速同步数字电路的性能优化，主要研究了在高性能系统中，时序优化在管道和一般顺序电路中的应用。研究工作的核心是在门级的重新定时方法。重定时是一种顺序逻辑优化技术，它在电路中重新定位存储元件，即边缘触发触发器和电平触发锁存器，以优化电路的定时行为。重新计时优化方法的使用，主要是设备尺寸，也正在研究中。在这个项目的教育部分，PI通过在教学中使用CAD工具，将CAD技术纳入大二的本科课程。在研究生阶段，他参与开发课程，支持现有课程，并为研究生提供建议。他还让本科生接触他的研究，以便更好地了解最新技术，并激励他们接受高等教育。他还通过电视向爱荷华州的网站教授课程，并通过卫星媒体在全国各地进行远程教育，为外展活动做出贡献。

This project is concerned with performance optimization of high- speed synchronous digital circuits It addresses the application of timing optimizations to pipelines and general sequential circuits in high-performance systems. The core of the research effort is directed towards the method of retiming at the gate level. Retiming is a sequential logic optimization technique that repositions memory elements, namely, edge-triggered flip-flops and level-triggered latches, within a circuits to optimize the timing behavior of the circuit. The use of retiming optimization methods, chiefly device sizing, is also being investigated. Under the educational part of this project, the PI is incorporating CAD techniques in the undergraduate program from the sophomore level by the use of CAD tools in teaching. At the graduate level, he is involved in developing courses, the supporting existing courses, and in advising graduate students. He is also exposing undergraduates to his research for a better appreciation of the state of the art, and to motivate them towards higher education. he is also contributing towards outreach activities by focusing towards distance education through teaching courses to sites in the state of Iowa via television, and around the country through the medium of satellite.