SHF: Small: Enchancing the Reliability of Mixed-Signal Integrated Circuits

基于硅的集成电路技术，无论是在当今的前沿技术，还是那些预计将在未来出现的技术，都是基于使用具有多个栅极的三维晶体管结构，如finfet、三极管或栅极全能器件。半导体行业面临着这些结构的一系列新挑战，特别是在可靠性和故障方面。本项目将研究克服这些挑战的有效解决方案，以促进下一代高性能集成电路的设计。除了研究之外，该项目还有一个教育组成部分，包括为混合信号电路可靠性的本科和研究生课程编写教学材料，并培训未来的科学家/工程师学习创造性解决问题的技能。具体而言，该项目解决了在数字和模拟部分混合信号集成电路设计中使用多门晶体管技术的问题，使用输入/输出（I/O）电路作为测试平台，评估了一组提出的方法，这些方法可以主动建模并减轻晶体管和互连线中的电路老化。将研究的具体老化机制包括偏置温度不稳定性、热载流子注入、栅氧化物击穿和电迁移。在多栅极晶体管技术中，热效应和热不均匀性的增加加剧了这些影响，因此开发将可靠性计算与热分析紧密结合的方法非常重要。这项工作将把这种效应在晶体管级的影响与混合信号块级联系起来，然后一直到系统级。所提出的技术将与片上补偿技术相结合，使电路对老化引起的性能漂移更加稳健。

Silicon-based integrated circuit technologies, both at the cutting edge today and those that are predicted to emerge in the future, are based on the use of three-dimensional transistor structures with multiple gates, such as finFETs, trigate transistors, or gate-all-around devices. The semiconductor industry faces a new set of challenges with these structures, particularly in relation to reliability and failures. This project will research effective solutions to overcome these challenges so as to facilitate the design of the next generation of high-performance integrated circuits. In addition to research, the project has an educational component that includes the development of instructional material for the undergraduate and graduate curriculum on reliability in mixed-signal circuits, and in training future scientists/engineers to learn creative problem solving skills.Specifically, this project addresses the use of multigate transistor technologies in the design of mixed-signal integrated circuits with both digital and analog parts, using the case of input/output (I/O) circuits as a testbed for evaluating a set of proposed approaches that proactively model and mitigate circuit aging in transistors and interconnect wires. Specific aging mechanisms that will be investigated include bias temperature instability, hot carrier injection, gate oxide breakdown, and electromigration. These effects are accentuated by the increased thermal effects and thermal nonuniformities seen in multigate transistor technologies, and it is important to develop methods that tightly integrate reliability computations with thermal analysis. The work will link the impact of such effects at the transistor level to the mixed-signal block level, and then up to the system level. The proposed techniques will act in conjunction with on-chip compensation techniques that make circuits more robust to aging-induced performance drifts.