Novel Sub-Threshold Methodologies for GaN Electronic Devices: A Study of Device Reliability and Degradation Mechanisms

氮化镓电力电子，特别是氮化镓/氮化镓高电子迁移率晶体管（HEMT）目前正在开发中，并开始应用于功率转换，雷达，卫星和通信应用。基于此的开关模式电力系统将提供更高的效率，从而形成低碳经济的关键使能技术。虽然这些设备的性能完全足以实现许多系统应用的颠覆性变化，但可靠性目前仍然存在问题，不仅在英国和欧洲，而且在美国和日本。本提案旨在开发一种新的电学方法来研究和理解GaN基hemt的可靠性，特别是确定GaN hemt运行过程中产生的电子陷阱的性质，以及影响其寿命的电子陷阱。该项目得到了英国、欧洲和美国主要行业（英国国际整流、德国弗劳恩霍夫研究所、德国UMS、美国TriQuint）的支持，并建立在布里斯托尔设备热成像和可靠性中心（CDTR）开发的GaN HEMT可靠性领域的领先专业知识基础上，该中心由EPSRC和美国海军研究办公室（ONR）资助，在布里斯托尔建立了各种研究项目。这项工作的重点将在于克服半导体器件中用于探测电子陷阱的高精度标准电容电压（CV）或电导技术无法在与实际应用相关的晶体管结构上执行的挑战。这是因为这些技术需要大型晶体管结构，以具有足够的电容来测量。现实的器件栅极长度短，因此电容过低，无法在1kHz-1MHz的典型测量频率下精确测量，而且在器件操作期间引入的任何损坏通常在太小的区域内，使用传统技术不易检测到。相比之下，可以应用于小型III-V场效应管器件（如电流- dlt或跨导色散）的方法分别使用非平衡脉冲技术，这种技术容易被误解，或者迄今为止只给出定性信息。支撑这一建议的一个关键观点是，通道内或通道附近的电子陷阱主要在低于掐断电压的设备中产生色散，这将在本计划中被利用。我们将开发一种动态跨导方法用于GaN HEMT可靠性分析，适用于小型HEMT器件，对栅漏电流不敏感。这种新的电学方法的发展提供了准平衡电容技术的优点，但在小型设备中，将首次实现对退化诱导陷阱特性的精确测量。噪声测量将补充这种新颖的陷阱分析，此外，我们将受益于我们在ONR资助的DRIFT计划中开发的脉冲电光陷阱分析技术。这项工作将促进对运行过程中GaN HEMT器件退化的理解，即器件可靠性，并将使英国保持在国际领先的半导体器件可靠性研究的前沿。所开发的方法也将直接适用于全球范围内迅速发展的III-V CMOS技术，用于缩放低功耗逻辑。

GaN power electronics, in particular, AlGaN/GaN high electron mobility transistors (HEMT) are currently being developed and starting to be applied for power conversion, radar, satellite and communication applications. Switched mode power systems based on this will deliver improved efficiency, hence forming a key enabling technology for the low carbon economy. Although performance of these devices is fully sufficient to enable disruptive changes for many system applications, reliability is presently still in question, not only in the UK and Europe, but also in the USA and Japan. This proposal aims at developing a new electrical methodology to study and understand reliability of GaN based HEMTs, in particular to identify the nature of electronic traps generated during the operation of GaN HEMTs, and which affect their lifetime. The programme is supported by key UK, European and US industries (International Rectifier UK, Fraunhofer Institute IAF Germany, UMS Germany, TriQuint USA), and builds on leading expertise in the field of GaN HEMT reliability developed at the Center for Device Thermography and Reliability (CDTR) in Bristol, established in various research programmes in Bristol funded by EPSRC and the US Office of Naval Research (ONR). The focus of this work will lie in overcoming the challenge that the highly accurate standard Capacitance-Voltage (CV) or Conductance technique for probing electronic traps in semiconductor devices cannot be performed on transistor structures relevant to real applications. This is because these techniques require large transistor structures to have enough capacitance to be measurable. Realistic devices have short gate length with consequently too low a capacitance to be accurately measured at the typical measurement frequency of 1kHz-1MHz, also any damage introduced into a device during device operation is typically in too small an area to be easily detectable using traditional techniques. In contrast, methods which can be applied to small III-V FET devices such as current-DLTS or transconductance dispersion respectively use a non-equilibrium pulse technique which is prone to misinterpretation, or have only given qualitative information to date. A key insight which underpins this proposal is that electronic traps in or near the channel primarily generate dispersion in a device below the pinch off voltage in the sub-threshold regime of operation which will be exploited in this programme. We will develop a dynamic transconductance method for GaN HEMT reliability analysis, suitable for small HEMT devices and insensitive to gate leakage currents. The development of this new electrical methodology which delivers the advantages of the quasi-equilibrium capacitance techniques but in small devices, will allow accurate measurements of degradation induced trap properties to be made for the first time. Noise measurements will complement this novel trap analysis, in additional we will benefit from the pulsed electrical-optical trapping analysis technique we developed in the ONR funded DRIFT programme. The work will advance the understanding of GaN HEMT device degradation during operation, i.e., device reliability, and will keep the UK at the forefront of internationally leading semiconductor device reliability research. The methodologies to be developed will also have direct applicability to the burgeoning worldwide effort in III-V CMOS technology for scaled low-power logic.