VLSI power management technology

现代超大规模集成电路芯片在最大性能状态下的功耗会导致芯片过热，甚至产生破坏性的后果。这在便携式多媒体和电信产品中尤其重要，因为在这些产品中，形状因子、冷却和电池寿命受到非常严格的限制。此外，由于固有的CMOS漏电流，还消耗了大量不需要的待机功率。电源管理是目前进一步提高超大规模集成电路性能和集成密度的最关键的使能技术之一。根据性能需求动态调整电源电压和时钟频率已经研究了10多年。以前的大多数工作只集中在VLSI芯片级的节能。高能效可变输出电源（DC-DC转换器）的设计通常被认为是微不足道的，并且是事后的想法。虽然在VLSI芯片级已经报道了显著的功率节省，但是在系统级的总体功率节省通常比预期的更差。

The power consumed by modern VLSI chips under maximum performance situation could cause over-heat and even become destructive. This is especially critical in portable multimedia and telecommunication products where form factor, cooling and battery life impose very stringent limitations. In addition, a substantial amount of unwanted standby power due to the inherent CMOS leakage current is also consumed. Power management is currently one of the most critical enabling technologies to further increase VLSI performance and integration density. Dynamically scaling of the power supply voltage and clock frequency according to performance needs has been investigated for more than 10 years. Most of the previous work focused only on saving power at the VLSI chip level. The design of the power efficient variable output power supplies (DC-DC Converters) is often assumed to be trivial and as an afterthought. While significant power saving has been reported at the VLSI chip level, the overall power saving at the system level is often worse than expected.